Struct stm32_metapac::rcc::regs::Bdcr

#[repr(transparent)]
pub struct Bdcr(pub u32);

Expand description

RCC Backup domain control register

Tuple Fields§

§0: u32

Implementations§

§

impl Bdcr

pub const fn lseon(&self) -> bool

LSE oscillator enabled Set and reset by software.

pub fn set_lseon(&mut self, val: bool)

LSE oscillator enabled Set and reset by software.

pub const fn lserdy(&self) -> bool

LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0.

pub fn set_lserdy(&mut self, val: bool)

LSE oscillator ready Set and reset by hardware to indicate when the LSE is stable. This bit needs 6 cycles of lse_ck clock to fall down after LSEON has been set to 0.

pub const fn lsebyp(&self) -> bool

LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1)

pub fn set_lsebyp(&mut self, val: bool)

LSE oscillator bypass Set and reset by software to bypass oscillator in debug mode. This bit must not be written when the LSE is enabled (by LSEON) or ready (LSERDY = 1)

pub const fn lsedrv(&self) -> Lsedrv

LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator. These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0).

pub fn set_lsedrv(&mut self, val: Lsedrv)

LSE oscillator driving capability Set by software to select the driving capability of the LSE oscillator. These bit can be written only if LSE oscillator is disabled (LSEON = 0 and LSERDY = 0).

pub const fn lsecsson(&self) -> bool

LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON.

pub fn set_lsecsson(&mut self, val: bool)

LSE clock security system enable Set by software to enable the clock security system on 32 kHz oscillator. LSECSSON must be enabled after LSE is enabled (LSEON enabled) and ready (LSERDY set by hardware) and after RTCSEL is selected. Once enabled, this bit cannot be disabled, except after a LSE failure detection (LSECSSD = 1). In that case the software must disable LSECSSON.

pub const fn lsecssd(&self) -> bool

LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator.

pub fn set_lsecssd(&mut self, val: bool)

LSE clock security system failure detection Set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator.

pub const fn lseext(&self) -> Lseext

low-speed external clock type in bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled.

pub fn set_lseext(&mut self, val: Lseext)

low-speed external clock type in bypass mode Set and reset by software to select the external clock type (analog or digital). The external clock must be enabled with the LSEON bit, to be used by the device. The LSEEXT bit can be written only if the LSE oscillator is disabled.

pub const fn rtcsel(&self) -> Rtcsel

RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST).

pub fn set_rtcsel(&mut self, val: Rtcsel)

RTC clock source selection Set by software to select the clock source for the RTC. These bits can be written only one time (except in case of failure detection on LSE). These bits must be written before LSECSSON is enabled. The VSWRST bit can be used to reset them, then it can be written one time again. If HSE is selected as RTC clock, this clock is lost when the system is in Stop mode or in case of a pin reset (NRST).

pub const fn rtcen(&self) -> bool

RTC clock enable Set and reset by software.

pub fn set_rtcen(&mut self, val: bool)

RTC clock enable Set and reset by software.

pub const fn vswrst(&self) -> bool

VSwitch domain software reset Set and reset by software.

pub fn set_vswrst(&mut self, val: bool)

VSwitch domain software reset Set and reset by software.

pub const fn lscoen(&self) -> bool

Low-speed clock output (LSCO) enable Set and cleared by software.

pub fn set_lscoen(&mut self, val: bool)

Low-speed clock output (LSCO) enable Set and cleared by software.

pub const fn lscosel(&self) -> Lscosel

Low-speed clock output selection Set and cleared by software.

pub fn set_lscosel(&mut self, val: Lscosel)

Low-speed clock output selection Set and cleared by software.

pub const fn lsion(&self) -> bool

LSI oscillator enable Set and cleared by software.

pub fn set_lsion(&mut self, val: bool)

LSI oscillator enable Set and cleared by software.

pub const fn lsirdy(&self) -> bool

LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0.

pub fn set_lsirdy(&mut self, val: bool)

LSI oscillator ready Set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after three internal low-speed oscillator clock cycles. This bit is set when the LSI is used by IWDG or RTC, even if LSION = 0.