Struct stm32_metapac::can::regs::Tocc
#[repr(transparent)]pub struct Tocc(pub u32);
Expand description
FDCAN timeout counter configuration register
Tuple Fields§
§0: u32
Implementations§
§impl Tocc
impl Tocc
pub const fn etoc(&self) -> bool
pub const fn etoc(&self) -> bool
Timeout counter enable. This is a protected write (P) bit, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1
pub fn set_etoc(&mut self, val: bool)
pub fn set_etoc(&mut self, val: bool)
Timeout counter enable. This is a protected write (P) bit, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1
pub const fn tos(&self) -> Tos
pub const fn tos(&self) -> Tos
Timeout select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC[TOP] and continues down-counting. When the timeout counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC[TOP]. Down-counting is started when the first FIFO element is stored. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1
pub fn set_tos(&mut self, val: Tos)
pub fn set_tos(&mut self, val: Tos)
Timeout select. When operating in Continuous mode, a write to TOCV presets the counter to the value configured by TOCC[TOP] and continues down-counting. When the timeout counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by TOCC[TOP]. Down-counting is started when the first FIFO element is stored. These are protected write (P) bits, write access is possible only when the bit 1 [CCE] and bit 0 [INIT] of CCCR register are set to 1