Struct M5isr
#[repr(transparent)]pub struct M5isr(pub u32);Expand description
RAMCFG memory interrupt status register.
Tuple Fields§
§0: u32Implementations§
§impl M5isr
impl M5isr
pub const fn sedc(&self) -> bool
pub const fn sedc(&self) -> bool
ECC single error detected and corrected Note: This bit is reserved and must be kept at reset value in SRAM1 interrupt status register.
pub fn set_sedc(&mut self, val: bool)
pub fn set_sedc(&mut self, val: bool)
ECC single error detected and corrected Note: This bit is reserved and must be kept at reset value in SRAM1 interrupt status register.
pub const fn ded(&self) -> bool
pub const fn ded(&self) -> bool
ECC double error detected Note: This bit is reserved and must be kept at reset value in SRAM1 interrupt status register.
pub fn set_ded(&mut self, val: bool)
pub fn set_ded(&mut self, val: bool)
ECC double error detected Note: This bit is reserved and must be kept at reset value in SRAM1 interrupt status register.
pub const fn srambusy(&self) -> bool
pub const fn srambusy(&self) -> bool
SRAM busy with erase operation Note: Depending on the SRAM, the erase operation can be performed due to software request, system reset if the option bit is enabled, tamper detection or product state regression. Refer to Table 9: Internal SRAMs features.
pub fn set_srambusy(&mut self, val: bool)
pub fn set_srambusy(&mut self, val: bool)
SRAM busy with erase operation Note: Depending on the SRAM, the erase operation can be performed due to software request, system reset if the option bit is enabled, tamper detection or product state regression. Refer to Table 9: Internal SRAMs features.