Enum stm32_metapac::i3c::vals::Rstact
#[repr(u8)]pub enum Rstact {
NORESET = 0,
FIRSTLEVEL = 1,
SECONDLEVEL = 2,
NORESETEITHER = 3,
}
Variants§
NORESET = 0
FIRSTLEVEL = 1
first level of reset: the application software must either: a) partially reset the peripheral, by a write and clear of the enable bit of the I3C configuration register (write EN = 0). This resets the I3C bus interface and the I3C kernel sub-parts, without modifying the content of the I3C APB registers (except the EN bit). b) fully reset the peripheral, including all its registers, via a write and set of the I3C reset control bit of the RCC (reset and clock controller) register.
SECONDLEVEL = 2
second level of reset: the application software must issue a warm reset, also known as a system reset. This (see Section 11: Reset and clock control (RCC)) has the same impact as a pin reset (NRST = 0): – the software writes and sets the SYSRESETREQ control bit of the AITR register, when the device is controlled by a Cortex®-M. – the software writes and sets SYSRST = 1 in the RCC_GRSTCSETR register, when the device is controlled by a Cortex®-A.
NORESETEITHER = 3
Implementations§
Trait Implementations§
§impl Ord for Rstact
impl Ord for Rstact
§impl PartialOrd for Rstact
impl PartialOrd for Rstact
impl Copy for Rstact
impl Eq for Rstact
impl StructuralPartialEq for Rstact
Auto Trait Implementations§
impl Freeze for Rstact
impl RefUnwindSafe for Rstact
impl Send for Rstact
impl Sync for Rstact
impl Unpin for Rstact
impl UnwindSafe for Rstact
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
source§unsafe fn clone_to_uninit(&self, dst: *mut T)
unsafe fn clone_to_uninit(&self, dst: *mut T)
clone_to_uninit
)