Struct stm32_metapac::i3c::regs::Timingr2

#[repr(transparent)]
pub struct Timingr2(pub u32);

I3C timing register 2.

Tuple Fields

0: u32

Implementations

impl Timingr2

pub const fn stallt(&self) -> bool

Controller clock stall on T-bit phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to prepare data to be sent.

pub fn set_stallt(&mut self, val: bool)

Controller clock stall on T-bit phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to prepare data to be sent.

pub const fn stalld(&self) -> bool

controller clock stall on PAR phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to read received data.

pub fn set_stalld(&mut self, val: bool)

controller clock stall on PAR phase of Data enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase (before 9th bit). This allows the target to read received data.

pub const fn stallc(&self) -> bool

controller clock stall on PAR phase of CCC enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase of common command code (before 9th bit). This allows the target to decode the command.

pub fn set_stallc(&mut self, val: bool)

controller clock stall on PAR phase of CCC enable The SCL is stalled during STALL x tSCLL_PP in the T-bit phase of common command code (before 9th bit). This allows the target to decode the command.

pub const fn stalla(&self) -> bool

controller clock stall enable on ACK phase The SCL is stalled (during tSCLL_STALLas defined by STALL) in the address ACK/NACK phase (before 9th bit). This allows the target to prepare data or the controller to respond to target interrupt.

pub fn set_stalla(&mut self, val: bool)

controller clock stall enable on ACK phase The SCL is stalled (during tSCLL_STALLas defined by STALL) in the address ACK/NACK phase (before 9th bit). This allows the target to prepare data or the controller to respond to target interrupt.

pub const fn stall(&self) -> u8

controller clock stall time, in number of kernel clock cycles tSCLL_STALL = STALL x tI3CCLK.

pub fn set_stall(&mut self, val: u8)

controller clock stall time, in number of kernel clock cycles tSCLL_STALL = STALL x tI3CCLK.

Trait Implementations

impl Clone for Timingr2

fn clone(&self) -> Timingr2

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Timingr2

fn default() -> Timingr2

Returns the “default value” for a type.

impl PartialEq for Timingr2

fn eq(&self, other: &Timingr2) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Timingr2

impl Eq for Timingr2

impl StructuralPartialEq for Timingr2