Struct stm32_metapac::timer::Tim1chCmp

pub struct Tim1chCmp { /* private fields */ }

1-channel with one complementary output timers

Implementations

impl Tim1chCmp

pub const unsafe fn from_ptr(ptr: *mut ()) -> Self

pub const fn as_ptr(&self) -> *mut ()

pub const fn cr1(self) -> Reg<Cr11ch, RW>

control register 1

pub const fn cr2(self) -> Reg<Cr21chCmp, RW>

control register 2

pub const fn dier(self) -> Reg<Dier1chCmp, RW>

DMA/Interrupt enable register

pub const fn sr(self) -> Reg<Sr1chCmp, RW>

status register

pub const fn egr(self) -> Reg<Egr1chCmp, W>

event generation register

pub const fn ccmr_input(self, n: usize) -> Reg<CcmrInput1ch, RW>

capture/compare mode register 1 (input mode)

pub const fn ccmr_output(self, n: usize) -> Reg<CcmrOutput1ch, RW>

capture/compare mode register 1 (output mode)

pub const fn ccer(self) -> Reg<Ccer1chCmp, RW>

capture/compare enable register

pub const fn cnt(self) -> Reg<CntCore, RW>

counter

pub const fn psc(self) -> Reg<u16, RW>

prescaler

pub const fn arr(self) -> Reg<ArrCore, RW>

auto-reload register (Dither mode disabled)

pub const fn arr_dither(self) -> Reg<ArrDitherCore, RW>

auto-reload register (Dither mode enabled)

pub const fn rcr(self) -> Reg<Rcr1chCmp, RW>

repetition counter register

pub const fn ccr(self, n: usize) -> Reg<Ccr1ch, RW>

capture/compare register x (x=1) (Dither mode disabled)

pub const fn ccr_dither(self, n: usize) -> Reg<CcrDither1ch, RW>

capture/compare register x (x=1) (Dither mode enabled)

pub const fn bdtr(self) -> Reg<Bdtr1chCmp, RW>

break and dead-time register

pub const fn dtr2(self) -> Reg<Dtr21chCmp, RW>

break and dead-time register

pub const fn tisel(self) -> Reg<Tisel1ch, RW>

input selection register

pub const fn af1(self) -> Reg<Af11chCmp, RW>

alternate function register 1

pub const fn af2(self) -> Reg<Af21chCmp, RW>

alternate function register 2

pub const fn or(self) -> Reg<u32, RW>

Option register 1 Note: Check Reference Manual to parse this register content

pub const fn dcr(self) -> Reg<Dcr1chCmp, RW>

DMA control register

pub const fn dmar(self) -> Reg<u32, RW>

DMA address for full transfer

Trait Implementations

impl Clone for Tim1chCmp

fn clone(&self) -> Tim1chCmp

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl PartialEq for Tim1chCmp

fn eq(&self, other: &Tim1chCmp) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Tim1chCmp

impl Eq for Tim1chCmp

impl Send for Tim1chCmp

impl StructuralPartialEq for Tim1chCmp

impl Sync for Tim1chCmp