Struct stm32_metapac::adc::regs::Isr
#[repr(transparent)]pub struct Isr(pub u32);Expand description
interrupt and status register
Tuple Fields§
§0: u32Implementations§
§impl Isr
impl Isr
pub const fn adrdy(&self) -> bool
pub const fn adrdy(&self) -> bool
ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it
pub fn set_adrdy(&mut self, val: bool)
pub fn set_adrdy(&mut self, val: bool)
ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it
pub const fn eosmp(&self) -> bool
pub const fn eosmp(&self) -> bool
End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase
pub fn set_eosmp(&mut self, val: bool)
pub fn set_eosmp(&mut self, val: bool)
End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase
pub const fn eoc(&self) -> bool
pub const fn eoc(&self) -> bool
End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register
pub fn set_eoc(&mut self, val: bool)
pub fn set_eoc(&mut self, val: bool)
End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register
pub const fn eos(&self) -> bool
pub const fn eos(&self) -> bool
End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it
pub fn set_eos(&mut self, val: bool)
pub fn set_eos(&mut self, val: bool)
End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it
pub const fn ovr(&self) -> bool
pub const fn ovr(&self) -> bool
overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it
pub fn set_ovr(&mut self, val: bool)
pub fn set_ovr(&mut self, val: bool)
overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it
pub const fn jeoc(&self) -> bool
pub const fn jeoc(&self) -> bool
Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register
pub fn set_jeoc(&mut self, val: bool)
pub fn set_jeoc(&mut self, val: bool)
Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register
pub const fn jeos(&self) -> bool
pub const fn jeos(&self) -> bool
Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it
pub fn set_jeos(&mut self, val: bool)
pub fn set_jeos(&mut self, val: bool)
Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it
pub const fn awd(&self, n: usize) -> bool
pub const fn awd(&self, n: usize) -> bool
Analog watchdog 1-3 flags. Set by hardware when the converted voltage crosses the values programmed in the corresponding fields LT and HT fields of the relevant TR register. It is cleared by software.
pub fn set_awd(&mut self, n: usize, val: bool)
pub fn set_awd(&mut self, n: usize, val: bool)
Analog watchdog 1-3 flags. Set by hardware when the converted voltage crosses the values programmed in the corresponding fields LT and HT fields of the relevant TR register. It is cleared by software.