Struct stm32_metapac::fmc::regs::Bwtr
#[repr(transparent)]pub struct Bwtr(pub u32);Expand description
SRAM/NOR-Flash write timing registers 1.
Tuple Fields§
§0: u32Implementations§
§impl Bwtr
impl Bwtr
pub const fn addset(&self) -> u8
pub const fn addset(&self) -> u8
Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: … Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1.
pub fn set_addset(&mut self, val: u8)
pub fn set_addset(&mut self, val: u8)
Address setup phase duration. These bits are written by software to define the duration of the address setup phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous accesses: … Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1.
pub const fn addhld(&self) -> u8
pub const fn addhld(&self) -> u8
Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 30 to Figure 33), used in asynchronous multiplexed accesses: … Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
pub fn set_addhld(&mut self, val: u8)
pub fn set_addhld(&mut self, val: u8)
Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure 30 to Figure 33), used in asynchronous multiplexed accesses: … Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration.
pub const fn datast(&self) -> u8
pub const fn datast(&self) -> u8
Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: …
pub fn set_datast(&mut self, val: u8)
pub fn set_datast(&mut self, val: u8)
Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure 21 to Figure 33), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses: …
pub const fn busturn(&self) -> u8
pub const fn busturn(&self) -> u8
Bus turnaround phase duration These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank. For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min …
pub fn set_busturn(&mut self, val: u8)
pub fn set_busturn(&mut self, val: u8)
Bus turnaround phase duration These bits are written by software to add a delay at the end of current write transaction to next transaction on the same bank. For FRAM memories, the bus turnaround delay should be configured to match the minimum tPC (precharge time) timings. The bus turnaround delay is inserted between any consecutive transactions on the same bank (read/read, write/write, read/write and write/read). The chip select is toggling between any consecutive accesses. (BUSTURN + 1)HCLK period ≥ tPC min …
pub const fn accmod(&self) -> Accmod
pub const fn accmod(&self) -> Accmod
Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
pub fn set_accmod(&mut self, val: Accmod)
pub fn set_accmod(&mut self, val: Accmod)
Access mode. Specifies the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1.
pub const fn datahld(&self) -> u8
pub const fn datahld(&self) -> u8
Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:.
pub fn set_datahld(&mut self, val: u8)
pub fn set_datahld(&mut self, val: u8)
Data hold phase duration These bits are written by software to define the duration of the data hold phase in HCLK cycles (refer to Figure 21 to Figure 33), used in asynchronous write accesses:.