Struct stm32_metapac::adc::regs::Cfgr2
#[repr(transparent)]pub struct Cfgr2(pub u32);
Expand description
configuration register 2
Tuple Fields§
§0: u32
Implementations§
§impl Cfgr2
impl Cfgr2
pub const fn rovse(&self) -> bool
pub const fn rovse(&self) -> bool
Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
pub fn set_rovse(&mut self, val: bool)
pub fn set_rovse(&mut self, val: bool)
Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
pub const fn jovse(&self) -> bool
pub const fn jovse(&self) -> bool
Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
pub fn set_jovse(&mut self, val: bool)
pub fn set_jovse(&mut self, val: bool)
Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing).
pub const fn ovsr(&self) -> Ovsr
pub const fn ovsr(&self) -> Ovsr
Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing).
pub fn set_ovsr(&mut self, val: Ovsr)
pub fn set_ovsr(&mut self, val: Ovsr)
Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing).
pub const fn ovss(&self) -> u8
pub const fn ovss(&self) -> u8
Oversampling shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. Other codes reserved Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing).
pub fn set_ovss(&mut self, val: u8)
pub fn set_ovss(&mut self, val: u8)
Oversampling shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. Other codes reserved Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing).
pub const fn trovs(&self) -> Trovs
pub const fn trovs(&self) -> Trovs
Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
pub fn set_trovs(&mut self, val: Trovs)
pub fn set_trovs(&mut self, val: Trovs)
Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
pub const fn rovsm(&self) -> Rovsm
pub const fn rovsm(&self) -> Rovsm
Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
pub fn set_rovsm(&mut self, val: Rovsm)
pub fn set_rovsm(&mut self, val: Rovsm)
Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
pub const fn swtrig(&self) -> Swtrig
pub const fn swtrig(&self) -> Swtrig
Software trigger bit for sampling time control trigger mode This bit is set and cleared by software to enable the bulb sampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
pub fn set_swtrig(&mut self, val: Swtrig)
pub fn set_swtrig(&mut self, val: Swtrig)
Software trigger bit for sampling time control trigger mode This bit is set and cleared by software to enable the bulb sampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
pub const fn bulb(&self) -> bool
pub const fn bulb(&self) -> bool
Bulb sampling mode This bit is set and cleared by software to enable the bulb sampling mode. SAMPTRIG bit must not be set when the BULB bit is set. The very first ADC conversion is performed with the sampling time specified in SMPx bits. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
pub fn set_bulb(&mut self, val: bool)
pub fn set_bulb(&mut self, val: bool)
Bulb sampling mode This bit is set and cleared by software to enable the bulb sampling mode. SAMPTRIG bit must not be set when the BULB bit is set. The very first ADC conversion is performed with the sampling time specified in SMPx bits. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
pub const fn smptrig(&self) -> bool
pub const fn smptrig(&self) -> bool
Sampling time control trigger mode This bit is set and cleared by software to enable the sampling time control trigger mode. The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge. EXTEN bit should be set to 01. BULB bit must not be set when the SMPTRIG bit is set. When EXTEN bit is set to 00, set SWTRIG to start the sampling and clear SWTRIG bit to start the conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
pub fn set_smptrig(&mut self, val: bool)
pub fn set_smptrig(&mut self, val: bool)
Sampling time control trigger mode This bit is set and cleared by software to enable the sampling time control trigger mode. The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge. EXTEN bit should be set to 01. BULB bit must not be set when the SMPTRIG bit is set. When EXTEN bit is set to 00, set SWTRIG to start the sampling and clear SWTRIG bit to start the conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing).
Trait Implementations§
impl Copy for Cfgr2
impl Eq for Cfgr2
impl StructuralPartialEq for Cfgr2
Auto Trait Implementations§
impl Freeze for Cfgr2
impl RefUnwindSafe for Cfgr2
impl Send for Cfgr2
impl Sync for Cfgr2
impl Unpin for Cfgr2
impl UnwindSafe for Cfgr2
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
source§unsafe fn clone_to_uninit(&self, dst: *mut T)
unsafe fn clone_to_uninit(&self, dst: *mut T)
clone_to_uninit
)