Struct stm32_metapac::syscfg::regs::Cfgr2
#[repr(transparent)]pub struct Cfgr2(pub u32);
Expand description
SBS Class B register
Tuple Fields§
§0: u32
Implementations§
§impl Cfgr2
impl Cfgr2
pub const fn cll(&self) -> bool
pub const fn cll(&self) -> bool
core lockup lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1/8/15/16/17 break inputs.
pub fn set_cll(&mut self, val: bool)
pub fn set_cll(&mut self, val: bool)
core lockup lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the lockup (HardFault) output of Cortex-M33 with TIM1/8/15/16/17 break inputs.
pub const fn sel(&self) -> bool
pub const fn sel(&self) -> bool
SRAM ECC error lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1/8/15/16/17.
pub fn set_sel(&mut self, val: bool)
pub fn set_sel(&mut self, val: bool)
SRAM ECC error lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the SRAM double ECC error signal with break input of TIM1/8/15/16/17.
pub const fn pvdl(&self) -> bool
pub const fn pvdl(&self) -> bool
PVD lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1/8/15/16/17 break inputs.
pub fn set_pvdl(&mut self, val: bool)
pub fn set_pvdl(&mut self, val: bool)
PVD lock This bit is set by software and cleared only by a system reset. It can be used to enable and lock the PVD connection with TIM1/8/15/16/17 break inputs.