Struct Tcr

#[repr(transparent)]
pub struct Tcr(pub u32);

Expand description

This register is used to configure the concerned channel.

Tuple Fields§

§0: u32

Implementations§

§

impl Tcr

pub const fn sinc(&self) -> Incmode

Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

0x00).

pub fn set_sinc(&mut self, val: Incmode)

Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0]

0x00).

pub const fn dinc(&self) -> Incmode

Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.

pub fn set_dinc(&mut self, val: Incmode)

Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden.

pub const fn ssize(&self) -> Wordsize

Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).

pub fn set_ssize(&mut self, val: Wordsize)

Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS < SSIZE and SINC ≠ 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1).

pub const fn dsize(&self) -> Wordsize

Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).

pub fn set_dsize(&mut self, val: Wordsize)

Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS < DSIZE and DINC ≠ 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1).

pub const fn sincos(&self) -> Wordsize

source increment offset size.

pub fn set_sincos(&mut self, val: Wordsize)

source increment offset size.

pub const fn dincos(&self) -> Wordsize

Destination increment offset.

pub fn set_dincos(&mut self, val: Wordsize)

Destination increment offset.

pub const fn sburst(&self) -> Burst

source burst transfer configuration.

pub fn set_sburst(&mut self, val: Burst)

source burst transfer configuration.

pub const fn dburst(&self) -> Burst

Destination burst transfer configuration.

pub fn set_dburst(&mut self, val: Burst)

Destination burst transfer configuration.

pub const fn tlen(&self) -> u8

buffer transfer lengh.

pub fn set_tlen(&mut self, val: u8)

buffer transfer lengh.

pub const fn pke(&self) -> bool

PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

pub fn set_pke(&mut self, val: bool)

PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0.

pub const fn pam(&self) -> Pam

Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

pub fn set_pam(&mut self, val: Pam)

Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0.

pub const fn trgm(&self) -> Trgm

Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.

pub fn set_trgm(&mut self, val: Trgm)

Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0.

pub const fn swrm(&self) -> bool

SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.

pub fn set_swrm(&mut self, val: bool)

SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0.

pub const fn bwm(&self) -> bool

Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.

pub fn set_bwm(&mut self, val: bool)

Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable.