Struct Isr
#[repr(transparent)]pub struct Isr(pub u32);Expand description
MDMA channel x interrupt/status register.
Tuple Fields§
§0: u32Implementations§
§impl Isr
impl Isr
pub const fn teif(&self) -> bool
pub const fn teif(&self) -> bool
Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
pub fn set_teif(&mut self, val: bool)
pub fn set_teif(&mut self, val: bool)
Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
pub const fn ctcif(&self) -> bool
pub const fn ctcif(&self) -> bool
Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
pub fn set_ctcif(&mut self, val: bool)
pub fn set_ctcif(&mut self, val: bool)
Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0.
pub const fn brtif(&self) -> bool
pub const fn brtif(&self) -> bool
Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
pub fn set_brtif(&mut self, val: bool)
pub fn set_brtif(&mut self, val: bool)
Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.
pub const fn btif(&self) -> bool
pub const fn btif(&self) -> bool
Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register.