Enum Ocm
#[repr(u8)]pub enum Ocm {
Show 16 variants
Frozen = 0,
ActiveOnMatch = 1,
InactiveOnMatch = 2,
Toggle = 3,
ForceInactive = 4,
ForceActive = 5,
PwmMode1 = 6,
PwmMode2 = 7,
RetrigerrableOpmMode1 = 8,
RetrigerrableOpmMode2 = 9,
Reserved1 = 10,
Reserved2 = 11,
CombinedPwmMode1 = 12,
CombinedPwmMode2 = 13,
Reserved3 = 14,
Reserved4 = 15,
}Variants§
Frozen = 0
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
ActiveOnMatch = 1
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
InactiveOnMatch = 2
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
Toggle = 3
OCyREF toggles when TIMx_CNT=TIMx_CCRy
ForceInactive = 4
OCyREF is forced low
ForceActive = 5
OCyREF is forced high
PwmMode1 = 6
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
PwmMode2 = 7
Inversely to PwmMode1
RetrigerrableOpmMode1 = 8
In up-counting mode, the channel is active until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.
RetrigerrableOpmMode2 = 9
In up-counting mode, the channel is inactive until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down- counting mode, the channel is active until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.
Reserved1 = 10
_reserved1
Reserved2 = 11
_reserved2
CombinedPwmMode1 = 12
tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref.
CombinedPwmMode2 = 13
tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref.
Reserved3 = 14
_reserved3
Reserved4 = 15
_reserved4