Struct stm32_metapac::pwr::regs::Sr1

#[repr(transparent)]
pub struct Sr1(pub u32);

PWR control status register 1.

Tuple Fields

0: u32

Implementations

impl Sr1

pub const fn actvos(&self) -> bool

VOS currently applied for V_CORE voltage scaling selection. These bit reflect the last VOS value applied to the PMU.

pub fn set_actvos(&mut self, val: bool)

VOS currently applied for V_CORE voltage scaling selection. These bit reflect the last VOS value applied to the PMU.

pub const fn actvosrdy(&self) -> bool

Voltage levels ready bit for currently used ACTVOS and SDHILEVEL This bit is set to 1 by hardware when the voltage regulator and the SMPS step-down converter are both disabled and Bypass mode is selected in PWR control register 2 (PWR_CSR2).

pub fn set_actvosrdy(&mut self, val: bool)

Voltage levels ready bit for currently used ACTVOS and SDHILEVEL This bit is set to 1 by hardware when the voltage regulator and the SMPS step-down converter are both disabled and Bypass mode is selected in PWR control register 2 (PWR_CSR2).

pub const fn pvdo(&self) -> Pvdo

Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. PLS[2:0] bits. bits. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.

pub fn set_pvdo(&mut self, val: Pvdo)

Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. PLS[2:0] bits. bits. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.

pub const fn avdo(&self) -> Avdo

Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.

pub fn set_avdo(&mut self, val: Avdo)

Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.

Trait Implementations

impl Clone for Sr1

fn clone(&self) -> Sr1

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Sr1

fn default() -> Sr1

Returns the “default value” for a type.

impl PartialEq for Sr1

fn eq(&self, other: &Sr1) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Sr1

impl Eq for Sr1

impl StructuralPartialEq for Sr1