Struct stm32_metapac::rtc::regs::Icsr

#[repr(transparent)]
pub struct Icsr(pub u32);

Expand description

Initialization control and status register

Tuple Fields§

§0: u32

Implementations§

§

impl Icsr

pub const fn wutwf(&self) -> bool

Wakeup timer write flag. This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in CR. It is cleared by hardware in initialization mode.

pub fn set_wutwf(&mut self, val: bool)

Wakeup timer write flag. This bit is set by hardware when WUT value can be changed, after the WUTE bit has been set to 0 in CR. It is cleared by hardware in initialization mode.

pub const fn shpf(&self) -> bool

Shift operation pending. This flag is set by hardware as soon as a shift operation is initiated by a write to the SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect.

pub fn set_shpf(&mut self, val: bool)

Shift operation pending. This flag is set by hardware as soon as a shift operation is initiated by a write to the SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect.

pub const fn inits(&self) -> bool

Initialization status flag. This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state).

pub fn set_inits(&mut self, val: bool)

Initialization status flag. This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state).

pub const fn rsf(&self) -> bool

Registers synchronization flag. This bit is set by hardware each time the calendar registers are copied into the shadow registers (SSR, TR and DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode.

pub fn set_rsf(&mut self, val: bool)

Registers synchronization flag. This bit is set by hardware each time the calendar registers are copied into the shadow registers (SSR, TR and DR). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF = 1), or when in bypass shadow register mode (BYPSHAD = 1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode.

pub const fn initf(&self) -> bool

Initialization flag. When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated.

pub fn set_initf(&mut self, val: bool)

Initialization flag. When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated.

pub const fn init(&self) -> bool

Initialization mode

pub fn set_init(&mut self, val: bool)

Initialization mode

pub const fn bin(&self) -> Bin

Binary mode

pub fn set_bin(&mut self, val: Bin)

Binary mode

pub const fn bcdu(&self) -> Bcdu

BCD update (BIN = 10 or 11) In mixed mode when both BCD calendar and binary extended counter are used (BIN = 10 or 11), the calendar second is incremented using the SSR Least Significant Bits.

pub fn set_bcdu(&mut self, val: Bcdu)

BCD update (BIN = 10 or 11) In mixed mode when both BCD calendar and binary extended counter are used (BIN = 10 or 11), the calendar second is incremented using the SSR Least Significant Bits.