Struct stm32_metapac::rcc::regs::Cfgr

#[repr(transparent)]
pub struct Cfgr(pub u32);

RCC clock configuration register.

Tuple Fields

0: u32

Implementations

impl Cfgr

pub const fn sw(&self) -> Sw

system clock switch Set and reset by software to select system clock source (sys_ck). Set by hardware in order to force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode or in case of failure of the HSE when used directly or indirectly as system clock. others: reserved.

pub fn set_sw(&mut self, val: Sw)

system clock switch Set and reset by software to select system clock source (sys_ck). Set by hardware in order to force the selection of the HSI or CSI (depending on STOPWUCK selection) when leaving a system Stop mode or in case of failure of the HSE when used directly or indirectly as system clock. others: reserved.

pub const fn sws(&self) -> Sw

system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. others: reserved.

pub fn set_sws(&mut self, val: Sw)

system clock switch status Set and reset by hardware to indicate which clock source is used as system clock. others: reserved.

pub const fn stopwuck(&self) -> Stopwuck

system clock selection after a wake up from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details. STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10).

pub fn set_stopwuck(&mut self, val: Stopwuck)

system clock selection after a wake up from system Stop Set and reset by software to select the system wakeup clock from system Stop. The selected clock is also used as emergency clock for the clock security system (CSS) on HSE. See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details. STOPWUCK must not be modified when CSS is enabled (by HSECSSON bit) and the system clock is HSE (SWS = 10) or a switch on HSE is requested (SW =10).

pub const fn stopkerwuck(&self) -> Stopkerwuck

kernel clock selection after a wake up from system Stop Set and reset by software to select the kernel wakeup clock from system Stop. See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details.

pub fn set_stopkerwuck(&mut self, val: Stopkerwuck)

kernel clock selection after a wake up from system Stop Set and reset by software to select the kernel wakeup clock from system Stop. See Section 1.: Dividers values can be changed on-the-fly. All dividers provide have 50% duty-cycles. for details.

pub const fn rtcpre(&self) -> u8

HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. …

pub fn set_rtcpre(&mut self, val: u8)

HSE division factor for RTC clock Set and cleared by software to divide the HSE to generate a clock for RTC. Caution: The software must set these bits correctly to ensure that the clock supplied to the RTC is lower than 1 MHz. These bits must be configured if needed before selecting the RTC clock source. …

pub const fn timpre(&self) -> Timpre

timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains. or 4, else it is equal to 4 x F_{rcc_pclkx_d2} Refer to Table 64: Ratio between clock timer and pclk for more details.

pub fn set_timpre(&mut self, val: Timpre)

timers clocks prescaler selection This bit is set and reset by software to control the clock frequency of all the timers connected to APB1 and APB2 domains. or 4, else it is equal to 4 x F_{rcc_pclkx_d2} Refer to Table 64: Ratio between clock timer and pclk for more details.

pub const fn mco1pre(&self) -> Mcopre

MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. …

pub fn set_mco1pre(&mut self, val: Mcopre)

MCO1 prescaler Set and cleared by software to configure the prescaler of the MCO1. Modification of this prescaler may generate glitches on MCO1. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. …

pub const fn mco1sel(&self) -> Mco1sel

Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved.

pub fn set_mco1sel(&mut self, val: Mco1sel)

Microcontroller clock output 1 Set and cleared by software. Clock source selection may generate glitches on MCO1. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved.

pub const fn mco2pre(&self) -> Mcopre

MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. …

pub fn set_mco2pre(&mut self, val: Mcopre)

MCO2 prescaler Set and cleared by software to configure the prescaler of the MCO2. Modification of this prescaler may generate glitches on MCO2. It is highly recommended to change this prescaler only after reset, before enabling the external oscillators and the PLLs. …

pub const fn mco2sel(&self) -> Mco2sel

microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved.

pub fn set_mco2sel(&mut self, val: Mco2sel)

microcontroller clock output 2 Set and cleared by software. Clock source selection may generate glitches on MCO2. It is highly recommended to configure these bits only after reset, before enabling the external oscillators and the PLLs. others: reserved.

Trait Implementations

impl Clone for Cfgr

fn clone(&self) -> Cfgr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Cfgr

fn default() -> Cfgr

Returns the “default value” for a type.

impl PartialEq for Cfgr

fn eq(&self, other: &Cfgr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Cfgr

impl Eq for Cfgr

impl StructuralPartialEq for Cfgr