Struct stm32_metapac::pwr::regs::Sr1
#[repr(transparent)]pub struct Sr1(pub u32);
Expand description
PWR control status register 1.
Tuple Fieldsยง
ยง0: u32
Implementationsยง
ยงimpl Sr1
impl Sr1
pub const fn actvos(&self) -> bool
pub const fn actvos(&self) -> bool
VOS currently applied for VCORE voltage scaling selection. These bit reflect the last VOS value applied to the PMU.
pub fn set_actvos(&mut self, val: bool)
pub fn set_actvos(&mut self, val: bool)
VOS currently applied for VCORE voltage scaling selection. These bit reflect the last VOS value applied to the PMU.
pub const fn actvosrdy(&self) -> bool
pub const fn actvosrdy(&self) -> bool
Voltage levels ready bit for currently used ACTVOS and SDHILEVEL This bit is set to 1 by hardware when the voltage regulator and the SMPS step-down converter are both disabled and Bypass mode is selected in PWR control register 2 (PWR_CSR2).
pub fn set_actvosrdy(&mut self, val: bool)
pub fn set_actvosrdy(&mut self, val: bool)
Voltage levels ready bit for currently used ACTVOS and SDHILEVEL This bit is set to 1 by hardware when the voltage regulator and the SMPS step-down converter are both disabled and Bypass mode is selected in PWR control register 2 (PWR_CSR2).
pub const fn pvdo(&self) -> Pvdo
pub const fn pvdo(&self) -> Pvdo
Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. PLS[2:0] bits. bits. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.
pub fn set_pvdo(&mut self, val: Pvdo)
pub fn set_pvdo(&mut self, val: Pvdo)
Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. PLS[2:0] bits. bits. Note: Since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.
pub const fn avdo(&self) -> Avdo
pub const fn avdo(&self) -> Avdo
Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.
pub fn set_avdo(&mut self, val: Avdo)
pub fn set_avdo(&mut self, val: Avdo)
Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.