Struct stm32_metapac::rcc::regs::Apbcfgr

#[repr(transparent)]
pub struct Apbcfgr(pub u32);

RCC APB clocks configuration register.

Tuple Fields

0: u32

Implementations

impl Apbcfgr

pub const fn ppre1(&self) -> Ppre

CPU domain APB1 prescaler Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE1 write. 0xx: rcc_pclk1 = sys_bus_ck (default after reset).

pub fn set_ppre1(&mut self, val: Ppre)

CPU domain APB1 prescaler Set and reset by software to control the division factor of rcc_pclk1. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE1 write. 0xx: rcc_pclk1 = sys_bus_ck (default after reset).

pub const fn ppre2(&self) -> Ppre

CPU domain APB2 prescaler Set and reset by software to control the division factor of rcc_pclk2. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE2 write. 0xx: rcc_pclk2 = sys_bus_ck (default after reset).

pub fn set_ppre2(&mut self, val: Ppre)

CPU domain APB2 prescaler Set and reset by software to control the division factor of rcc_pclk2. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE2 write. 0xx: rcc_pclk2 = sys_bus_ck (default after reset).

pub const fn ppre4(&self) -> Ppre

CPU domain APB4 prescaler Set and reset by software to control the division factor of rcc_pclk4. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE4 write. 0xx: rcc_pclk4 = sys_bus_ck (default after reset).

pub fn set_ppre4(&mut self, val: Ppre)

CPU domain APB4 prescaler Set and reset by software to control the division factor of rcc_pclk4. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE4 write. 0xx: rcc_pclk4 = sys_bus_ck (default after reset).

pub const fn ppre5(&self) -> Ppre

CPU domain APB5 prescaler Set and reset by software to control the division factor of rcc_pclk5. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE5 write. 0xx: rcc_pclk5 = sys_bus_ck (default after reset).

pub fn set_ppre5(&mut self, val: Ppre)

CPU domain APB5 prescaler Set and reset by software to control the division factor of rcc_pclk5. The clock is divided by the new prescaler factor from 1 to 16 cycles of sys_bus_ck after PPRE5 write. 0xx: rcc_pclk5 = sys_bus_ck (default after reset).

Trait Implementations

impl Clone for Apbcfgr

fn clone(&self) -> Apbcfgr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Apbcfgr

fn default() -> Apbcfgr

Returns the “default value” for a type.

impl PartialEq for Apbcfgr

fn eq(&self, other: &Apbcfgr) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Apbcfgr

impl Eq for Apbcfgr

impl StructuralEq for Apbcfgr

impl StructuralPartialEq for Apbcfgr