Struct stm32_metapac::rcc::regs::Bmcfgr
#[repr(transparent)]pub struct Bmcfgr(pub u32);
Expand description
RCC AHB clock configuration register.
Tuple Fieldsยง
ยง0: u32
Implementationsยง
ยงimpl Bmcfgr
impl Bmcfgr
pub const fn bmpre(&self) -> Hpre
pub const fn bmpre(&self) -> Hpre
Bus matrix clock prescaler Set and reset by software to control the division factor of rcc_hclk[5:1] and rcc_aclk. This group of clocks is also named sys_bus_ck. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: sys_bus_ck= sys_cpu_ck (default after reset) Note: The clocks are divided by the new prescaler factor from 1 to 16 periods of the slowest APB clock among rcc_pclk1,2,4,5 after BMPRE update. Note: Note also that frequency of rcc_hclk[5:1] = rcc_aclk = sys_bus_ck.
pub fn set_bmpre(&mut self, val: Hpre)
pub fn set_bmpre(&mut self, val: Hpre)
Bus matrix clock prescaler Set and reset by software to control the division factor of rcc_hclk[5:1] and rcc_aclk. This group of clocks is also named sys_bus_ck. Changing this division ratio has an impact on the frequency of all bus matrix clocks. 0xxx: sys_bus_ck= sys_cpu_ck (default after reset) Note: The clocks are divided by the new prescaler factor from 1 to 16 periods of the slowest APB clock among rcc_pclk1,2,4,5 after BMPRE update. Note: Note also that frequency of rcc_hclk[5:1] = rcc_aclk = sys_bus_ck.