Struct stm32_metapac::rcc::regs::Cdcfgr
#[repr(transparent)]pub struct Cdcfgr(pub u32);
Expand description
RCC CPU domain clock configuration register.
Tuple Fieldsยง
ยง0: u32
Implementationsยง
ยงimpl Cdcfgr
impl Cdcfgr
pub const fn cpre(&self) -> Hpre
pub const fn cpre(&self) -> Hpre
CPU domain core prescaler Set and reset by software to control the CPU clock division factor. Changing this division ratio has an impact on the frequency of the CPU clock and all bus matrix clocks. After changing this prescaler value, it takes up to 16 periods of the slowest APB clock before the new division ratio is taken into account. The application can check if the new division factor is taken into account by reading back this register. 0xxx: sys_ck not divided (default after reset).
pub fn set_cpre(&mut self, val: Hpre)
pub fn set_cpre(&mut self, val: Hpre)
CPU domain core prescaler Set and reset by software to control the CPU clock division factor. Changing this division ratio has an impact on the frequency of the CPU clock and all bus matrix clocks. After changing this prescaler value, it takes up to 16 periods of the slowest APB clock before the new division ratio is taken into account. The application can check if the new division factor is taken into account by reading back this register. 0xxx: sys_ck not divided (default after reset).