Struct stm32_metapac::rcc::regs::Cifr
#[repr(transparent)]pub struct Cifr(pub u32);Expand description
RCC clock source interrupt flag register.
Tuple Fields§
§0: u32Implementations§
§impl Cifr
impl Cifr
pub const fn lsirdyf(&self) -> bool
pub const fn lsirdyf(&self) -> bool
LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.
pub fn set_lsirdyf(&mut self, val: bool)
pub fn set_lsirdyf(&mut self, val: bool)
LSI ready interrupt flag Reset by software by writing LSIRDYC bit. Set by hardware when the LSI clock becomes stable and LSIRDYIE is set.
pub const fn lserdyf(&self) -> bool
pub const fn lserdyf(&self) -> bool
LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set.
pub fn set_lserdyf(&mut self, val: bool)
pub fn set_lserdyf(&mut self, val: bool)
LSE ready interrupt flag Reset by software by writing LSERDYC bit. Set by hardware when the LSE clock becomes stable and LSERDYIE is set.
pub const fn hsirdyf(&self) -> bool
pub const fn hsirdyf(&self) -> bool
HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set.
pub fn set_hsirdyf(&mut self, val: bool)
pub fn set_hsirdyf(&mut self, val: bool)
HSI ready interrupt flag Reset by software by writing HSIRDYC bit. Set by hardware when the HSI clock becomes stable and HSIRDYIE is set.
pub const fn hserdyf(&self) -> bool
pub const fn hserdyf(&self) -> bool
HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set.
pub fn set_hserdyf(&mut self, val: bool)
pub fn set_hserdyf(&mut self, val: bool)
HSE ready interrupt flag Reset by software by writing HSERDYC bit. Set by hardware when the HSE clock becomes stable and HSERDYIE is set.
pub const fn csirdyf(&self) -> bool
pub const fn csirdyf(&self) -> bool
CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set.
pub fn set_csirdyf(&mut self, val: bool)
pub fn set_csirdyf(&mut self, val: bool)
CSI ready interrupt flag Reset by software by writing CSIRDYC bit. Set by hardware when the CSI clock becomes stable and CSIRDYIE is set.
pub const fn hsi48rdyf(&self) -> bool
pub const fn hsi48rdyf(&self) -> bool
HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set.
pub fn set_hsi48rdyf(&mut self, val: bool)
pub fn set_hsi48rdyf(&mut self, val: bool)
HSI48 ready interrupt flag Reset by software by writing HSI48RDYC bit. Set by hardware when the HSI48 clock becomes stable and HSI48RDYIE is set.
pub const fn pllrdyf(&self, n: usize) -> bool
pub const fn pllrdyf(&self, n: usize) -> bool
PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set.
pub fn set_pllrdyf(&mut self, n: usize, val: bool)
pub fn set_pllrdyf(&mut self, n: usize, val: bool)
PLL1 ready interrupt flag Reset by software by writing PLL1RDYC bit. Set by hardware when the PLL1 locks and PLL1RDYIE is set.
pub const fn lsecssf(&self) -> bool
pub const fn lsecssf(&self) -> bool
LSE clock security system interrupt flag Reset by software by writing LSECSSC bit. Set by hardware when a failure is detected on the external 32 kHz oscillator and LSECSSIE is set.
pub fn set_lsecssf(&mut self, val: bool)
pub fn set_lsecssf(&mut self, val: bool)
LSE clock security system interrupt flag Reset by software by writing LSECSSC bit. Set by hardware when a failure is detected on the external 32 kHz oscillator and LSECSSIE is set.
pub const fn hsecssf(&self) -> bool
pub const fn hsecssf(&self) -> bool
HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure.
pub fn set_hsecssf(&mut self, val: bool)
pub fn set_hsecssf(&mut self, val: bool)
HSE clock security system interrupt flag Reset by software by writing HSECSSC bit. Set by hardware in case of HSE clock failure.