Struct stm32_metapac::rcc::regs::Pllckselr
#[repr(transparent)]pub struct Pllckselr(pub u32);
Expand description
RCC PLLs clock source selection register.
Tuple Fieldsยง
ยง0: u32
Implementationsยง
ยงimpl Pllckselr
impl Pllckselr
pub const fn pllsrc(&self) -> Pllsrc
pub const fn pllsrc(&self) -> Pllsrc
DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, PLLSRC must be set to 11.
pub fn set_pllsrc(&mut self, val: Pllsrc)
pub fn set_pllsrc(&mut self, val: Pllsrc)
DIVMx and PLLs clock source selection Set and reset by software to select the PLL clock source. These bits can be written only when all PLLs are disabled. In order to save power, when no PLL is used, PLLSRC must be set to 11.
pub const fn divm(&self, n: usize) -> Pllm
pub const fn divm(&self, n: usize) -> Pllm
prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. โฆ โฆ
pub fn set_divm(&mut self, n: usize, val: Pllm)
pub fn set_divm(&mut self, n: usize, val: Pllm)
prescaler for PLL1 Set and cleared by software to configure the prescaler of the PLL1. The hardware does not allow any modification of this prescaler when PLL1 is enabled (PLL1ON = 1). In order to save power when PLL1 is not used, the value of DIVM1 must be set to 0. โฆ โฆ