Struct stm32_metapac::rcc::regs::Plldivr2
#[repr(transparent)]pub struct Plldivr2(pub u32);
Expand description
RCC PLL1 dividers configuration register 2.
Tuple Fieldsยง
ยง0: u32
Implementationsยง
ยงimpl Plldivr2
impl Plldivr2
pub const fn plls(&self) -> Plldivst
pub const fn plls(&self) -> Plldivst
PLL1 DIVS division factor Set and reset by software to control the frequency of the pll1_s_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVS+1) is even, With VCOH, for all DIVS values These bits can be written only when the PLL1DIVSEN = 0.
pub fn set_plls(&mut self, val: Plldivst)
pub fn set_plls(&mut self, val: Plldivst)
PLL1 DIVS division factor Set and reset by software to control the frequency of the pll1_s_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVS+1) is even, With VCOH, for all DIVS values These bits can be written only when the PLL1DIVSEN = 0.
pub const fn pllt(&self) -> Plldivst
pub const fn pllt(&self) -> Plldivst
PLL1 DIVT division factor Set and reset by software to control the frequency of the pll1_t_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVT+1) is even, With VCOH, for all DIVT values These bits can be written only when the PLL1DIVTEN = 0.
pub fn set_pllt(&mut self, val: Plldivst)
pub fn set_pllt(&mut self, val: Plldivst)
PLL1 DIVT division factor Set and reset by software to control the frequency of the pll1_t_ck clock. This post-divider performs divisions with 50% duty-cycle. The duty-cycle of 50% is guaranteed only in the following conditions: With VCOL, if (DIVT+1) is even, With VCOH, for all DIVT values These bits can be written only when the PLL1DIVTEN = 0.