Struct stm32_metapac::sdmmc::regs::Idmactrlr
#[repr(transparent)]pub struct Idmactrlr(pub u32);Expand description
The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.
Tuple Fields§
§0: u32Implementations§
§impl Idmactrlr
impl Idmactrlr
pub const fn idmaen(&self) -> bool
pub const fn idmaen(&self) -> bool
IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
pub fn set_idmaen(&mut self, val: bool)
pub fn set_idmaen(&mut self, val: bool)
IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
pub const fn idmabmode(&self) -> bool
pub const fn idmabmode(&self) -> bool
Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
pub fn set_idmabmode(&mut self, val: bool)
pub fn set_idmabmode(&mut self, val: bool)
Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0).
pub const fn idmabact(&self) -> bool
pub const fn idmabact(&self) -> bool
Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware.
pub fn set_idmabact(&mut self, val: bool)
pub fn set_idmabact(&mut self, val: bool)
Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware.