Struct stm32_metapac::syscfg::regs::Bklockr
#[repr(transparent)]pub struct Bklockr(pub u32);Expand description
SBS break lockup register.
Tuple Fields§
§0: u32Implementations§
§impl Bklockr
impl Bklockr
pub const fn pvd_bl(&self) -> bool
pub const fn pvd_bl(&self) -> bool
PVD break lock This bit is set by SW and cleared only by a system reset. it can be used to enable and lock the connection to TIM1/8/15/16/17Break input as well as the PVDE and PLS[2:0] bitfields in the PWR_CR1 register. Once set, this bit is cleared only by a system reset.
pub fn set_pvd_bl(&mut self, val: bool)
pub fn set_pvd_bl(&mut self, val: bool)
PVD break lock This bit is set by SW and cleared only by a system reset. it can be used to enable and lock the connection to TIM1/8/15/16/17Break input as well as the PVDE and PLS[2:0] bitfields in the PWR_CR1 register. Once set, this bit is cleared only by a system reset.
pub const fn flashecc_bl(&self) -> bool
pub const fn flashecc_bl(&self) -> bool
Flash ECC error break lock Set this bit to enable and lock the connection between embedded flash memory ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
pub fn set_flashecc_bl(&mut self, val: bool)
pub fn set_flashecc_bl(&mut self, val: bool)
Flash ECC error break lock Set this bit to enable and lock the connection between embedded flash memory ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
pub const fn cm7lckup_bl(&self) -> bool
pub const fn cm7lckup_bl(&self) -> bool
Cortex-M7 lockup break lock Set this bit to enable and lock the connection between the Cortex-M7 lockup (HardFault) output and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
pub fn set_cm7lckup_bl(&mut self, val: bool)
pub fn set_cm7lckup_bl(&mut self, val: bool)
Cortex-M7 lockup break lock Set this bit to enable and lock the connection between the Cortex-M7 lockup (HardFault) output and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
pub const fn bkramecc_bl(&self) -> bool
pub const fn bkramecc_bl(&self) -> bool
Backup RAM ECC error break lock Set this bit to enable and lock the connection between backup RAM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
pub fn set_bkramecc_bl(&mut self, val: bool)
pub fn set_bkramecc_bl(&mut self, val: bool)
Backup RAM ECC error break lock Set this bit to enable and lock the connection between backup RAM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
pub const fn dtcmecc_bl(&self) -> bool
pub const fn dtcmecc_bl(&self) -> bool
DTCM ECC error break lock Set this bit to enable and lock the connection between DTCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. Note: The DTCM0 and DTCM1 are Ored to give DTCMECC.
pub fn set_dtcmecc_bl(&mut self, val: bool)
pub fn set_dtcmecc_bl(&mut self, val: bool)
DTCM ECC error break lock Set this bit to enable and lock the connection between DTCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset. Note: The DTCM0 and DTCM1 are Ored to give DTCMECC.
pub const fn itcmecc_bl(&self) -> bool
pub const fn itcmecc_bl(&self) -> bool
ITCM ECC error break lock Set this bit to enable and lock the connection between ITCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
pub fn set_itcmecc_bl(&mut self, val: bool)
pub fn set_itcmecc_bl(&mut self, val: bool)
ITCM ECC error break lock Set this bit to enable and lock the connection between ITCM ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
pub const fn aram3ecc_bl(&self) -> bool
pub const fn aram3ecc_bl(&self) -> bool
AXIRAM3 ECC error break lock Set this bit to enable and lock the connection between AXIRAM3 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set this bit is cleared only by a system reset.
pub fn set_aram3ecc_bl(&mut self, val: bool)
pub fn set_aram3ecc_bl(&mut self, val: bool)
AXIRAM3 ECC error break lock Set this bit to enable and lock the connection between AXIRAM3 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set this bit is cleared only by a system reset.
pub const fn aram1ecc_bl(&self) -> bool
pub const fn aram1ecc_bl(&self) -> bool
AXIRAM1 ECC error break lock Set this bit to enable and lock the connection between AXIRAM1 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.
pub fn set_aram1ecc_bl(&mut self, val: bool)
pub fn set_aram1ecc_bl(&mut self, val: bool)
AXIRAM1 ECC error break lock Set this bit to enable and lock the connection between AXIRAM1 ECC double error detection flag and break inputs of TIM1/15/16/17 peripherals. Once set, this bit is cleared only by a system reset.