Struct stm32_metapac::ucpd::regs::Cfgr1
#[repr(transparent)]pub struct Cfgr1(pub u32);Expand description
configuration register 1
Tuple Fields§
§0: u32Implementations§
§impl Cfgr1
impl Cfgr1
pub const fn hbitclkdiv(&self) -> u8
pub const fn hbitclkdiv(&self) -> u8
Division ratio for producing half-bit clock The bitfield determines the division ratio (the bitfield value plus one) of a clk divider producing half-bit clock (hbit_clk).
pub fn set_hbitclkdiv(&mut self, val: u8)
pub fn set_hbitclkdiv(&mut self, val: u8)
Division ratio for producing half-bit clock The bitfield determines the division ratio (the bitfield value plus one) of a clk divider producing half-bit clock (hbit_clk).
pub const fn ifrgap(&self) -> u8
pub const fn ifrgap(&self) -> u8
Division ratio for producing inter-frame gap timer clock The bitfield determines the division ratio (the bitfield value minus one) of a clk divider producing inter-frame gap timer clock (tInterFrameGap). The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal.
pub fn set_ifrgap(&mut self, val: u8)
pub fn set_ifrgap(&mut self, val: u8)
Division ratio for producing inter-frame gap timer clock The bitfield determines the division ratio (the bitfield value minus one) of a clk divider producing inter-frame gap timer clock (tInterFrameGap). The division ratio 15 is to apply for Tx clock at the USB PD 2.0 specification nominal value. The division ratios below 15 are to apply for Tx clock below nominal, and the division ratios above 15 for Tx clock above nominal.
pub const fn transwin(&self) -> u8
pub const fn transwin(&self) -> u8
Transition window duration The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval. Set a value that produces an interval of 12 to 20 us, taking into account the clk frequency and the HBITCLKDIV[5:0] bitfield setting.
pub fn set_transwin(&mut self, val: u8)
pub fn set_transwin(&mut self, val: u8)
Transition window duration The bitfield determines the division ratio (the bitfield value minus one) of a hbit_clk divider producing tTransitionWindow interval. Set a value that produces an interval of 12 to 20 us, taking into account the clk frequency and the HBITCLKDIV[5:0] bitfield setting.
pub const fn psc_usbpdclk(&self) -> PscUsbpdclk
pub const fn psc_usbpdclk(&self) -> PscUsbpdclk
Pre-scaler division ratio for generating clk The bitfield determines the division ratio of a kernel clock pre-scaler producing peripheral clock (clk). It is recommended to use the pre-scaler so as to set the clk frequency in the range from 6 to 9 MHz.
pub fn set_psc_usbpdclk(&mut self, val: PscUsbpdclk)
pub fn set_psc_usbpdclk(&mut self, val: PscUsbpdclk)
Pre-scaler division ratio for generating clk The bitfield determines the division ratio of a kernel clock pre-scaler producing peripheral clock (clk). It is recommended to use the pre-scaler so as to set the clk frequency in the range from 6 to 9 MHz.
pub const fn rxordseten(&self) -> u16
pub const fn rxordseten(&self) -> u16
Receiver ordered set enable The bitfield determines the types of ordered sets that the receiver must detect. When set/cleared, each bit enables/disables a specific function: 0bxxxxxxxx1: SOP detect enabled 0bxxxxxxx1x: SOP’ detect enabled 0bxxxxxx1xx: SOP’’ detect enabled 0bxxxxx1xxx: Hard Reset detect enabled 0bxxxx1xxxx: Cable Detect reset enabled 0bxxx1xxxxx: SOP’_Debug enabled 0bxx1xxxxxx: SOP’’_Debug enabled 0bx1xxxxxxx: SOP extension#1 enabled 0b1xxxxxxxx: SOP extension#2 enabled
pub fn set_rxordseten(&mut self, val: u16)
pub fn set_rxordseten(&mut self, val: u16)
Receiver ordered set enable The bitfield determines the types of ordered sets that the receiver must detect. When set/cleared, each bit enables/disables a specific function: 0bxxxxxxxx1: SOP detect enabled 0bxxxxxxx1x: SOP’ detect enabled 0bxxxxxx1xx: SOP’’ detect enabled 0bxxxxx1xxx: Hard Reset detect enabled 0bxxxx1xxxx: Cable Detect reset enabled 0bxxx1xxxxx: SOP’_Debug enabled 0bxx1xxxxxx: SOP’’_Debug enabled 0bx1xxxxxxx: SOP extension#1 enabled 0b1xxxxxxxx: SOP extension#2 enabled
pub const fn txdmaen(&self) -> bool
pub const fn txdmaen(&self) -> bool
Transmission DMA mode enable When set, the bit enables DMA mode for transmission.
pub fn set_txdmaen(&mut self, val: bool)
pub fn set_txdmaen(&mut self, val: bool)
Transmission DMA mode enable When set, the bit enables DMA mode for transmission.
pub const fn rxdmaen(&self) -> bool
pub const fn rxdmaen(&self) -> bool
Reception DMA mode enable When set, the bit enables DMA mode for reception.
pub fn set_rxdmaen(&mut self, val: bool)
pub fn set_rxdmaen(&mut self, val: bool)
Reception DMA mode enable When set, the bit enables DMA mode for reception.
pub const fn ucpden(&self) -> bool
pub const fn ucpden(&self) -> bool
peripheral enable General enable of the peripheral. Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state.
pub fn set_ucpden(&mut self, val: bool)
pub fn set_ucpden(&mut self, val: bool)
peripheral enable General enable of the peripheral. Upon disabling, the peripheral instantly quits any ongoing activity and all control bits and bitfields default to their reset values. They must be set to their desired values each time the peripheral transits from disabled to enabled state.