Struct stm32_metapac::pwr::regs::Sr2

#[repr(transparent)]
pub struct Sr2(pub u32);

Expand description

Power status register 2

Tuple Fields§

§0: u32

Implementations§

§

impl Sr2

pub const fn flash_rdy(&self) -> bool

Flash ready flag This bit is set by hardware to indicate when the flash memory is readey to be accessed after wake-up from power-down. To place the flash memory in power-down, set either FPD_LPRUN, FPD_LPSLP or FPD_STP bits. Note : If the system boots from SRAM, the user application must wait until the FLASH_RDY bit is set, prior to jumping to flash memory.

pub fn set_flash_rdy(&mut self, val: bool)

Flash ready flag This bit is set by hardware to indicate when the flash memory is readey to be accessed after wake-up from power-down. To place the flash memory in power-down, set either FPD_LPRUN, FPD_LPSLP or FPD_STP bits. Note : If the system boots from SRAM, the user application must wait until the FLASH_RDY bit is set, prior to jumping to flash memory.

pub const fn reglps(&self) -> bool

Low-power regulator started This bit provides the information whether the low-power regulator is ready after a power-on reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wake-up from Standby mode time may be increased.

pub fn set_reglps(&mut self, val: bool)

Low-power regulator started This bit provides the information whether the low-power regulator is ready after a power-on reset or a Standby/Shutdown. If the Standby mode is entered while REGLPS bit is still cleared, the wake-up from Standby mode time may be increased.

pub const fn reglpf(&self) -> bool

Low-power regulator flag This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. This bit is cleared by hardware when the regulator is ready.

pub fn set_reglpf(&mut self, val: bool)

Low-power regulator flag This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits from the Low-power run mode, this bit remains at 1 until the regulator is ready in main mode. A polling on this bit must be done before increasing the product frequency. This bit is cleared by hardware when the regulator is ready.

pub const fn vosf(&self) -> bool

Voltage scaling flag A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register.

pub fn set_vosf(&mut self, val: bool)

Voltage scaling flag A delay is required for the internal regulator to be ready after the voltage scaling has been changed. VOSF indicates that the regulator reached the voltage level defined with VOS bits of the PWR_CR1 register.

pub const fn pvdo(&self) -> bool

Programmable voltage detector output

pub fn set_pvdo(&mut self, val: bool)

Programmable voltage detector output

pub const fn pvmo1(&self) -> bool

Peripheral voltage monitoring output: V_DDUSB vs. 1.2 V Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wake-up time.

pub fn set_pvmo1(&mut self, val: bool)

Peripheral voltage monitoring output: V_DDUSB vs. 1.2 V Note: PVMO1 is cleared when PVM1 is disabled (PVME1 = 0). After enabling PVM1, the PVM1 output is valid after the PVM1 wake-up time.

pub const fn pvmo3(&self) -> bool

Peripheral voltage monitoring output: V_DDA vs. 1.621V Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the PVM3 output is valid after the PVM3 wake-up time.

pub fn set_pvmo3(&mut self, val: bool)

Peripheral voltage monitoring output: V_DDA vs. 1.621V Note: PVMO3 is cleared when PVM3 is disabled (PVME3 = 0). After enabling PVM3, the PVM3 output is valid after the PVM3 wake-up time.

pub const fn pvmo4(&self) -> bool

Peripheral voltage monitoring output: V_DDA vs. 2.21V Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the PVM4 output is valid after the PVM4 wake-up time.

pub fn set_pvmo4(&mut self, val: bool)

Peripheral voltage monitoring output: V_DDA vs. 2.21V Note: PVMO4 is cleared when PVM4 is disabled (PVME4 = 0). After enabling PVM4, the PVM4 output is valid after the PVM4 wake-up time.