Struct stm32_metapac::rcc::regs::Pllcfgr
#[repr(transparent)]pub struct Pllcfgr(pub u32);
Expand description
PLL configuration register.
Tuple Fields§
§0: u32
Implementations§
§impl Pllcfgr
impl Pllcfgr
pub const fn pllsrc(&self) -> Pllsrc
pub const fn pllsrc(&self) -> Pllsrc
PLL input clock source This bit is controlled by software to select PLL clock source, as follows: The bitfield can be written only when the PLL is disabled. When the PLL is not used, selecting 00 allows saving power.
pub fn set_pllsrc(&mut self, val: Pllsrc)
pub fn set_pllsrc(&mut self, val: Pllsrc)
PLL input clock source This bit is controlled by software to select PLL clock source, as follows: The bitfield can be written only when the PLL is disabled. When the PLL is not used, selecting 00 allows saving power.
pub const fn pllm(&self) -> Pllm
pub const fn pllm(&self) -> Pllm
Division factor M of the PLL input clock divider This bit is controlled by software to divide the PLL input clock before the actual phase-locked loop, as follows: The bitfield can be written only when the PLL is disabled. Caution: The software must set these bits so that the PLL input frequency after the /M divider is between 2.66 and 161MHz.
pub fn set_pllm(&mut self, val: Pllm)
pub fn set_pllm(&mut self, val: Pllm)
Division factor M of the PLL input clock divider This bit is controlled by software to divide the PLL input clock before the actual phase-locked loop, as follows: The bitfield can be written only when the PLL is disabled. Caution: The software must set these bits so that the PLL input frequency after the /M divider is between 2.66 and 161MHz.
pub const fn plln(&self) -> Plln
pub const fn plln(&self) -> Plln
PLL frequency multiplication factor N This bit is controlled by software to set the division factor of the fVCO feedback divider (that determines the PLL multiplication ratio) as follows: … … The bitfield can be written only when the PLL is disabled. Caution: The software must set these bits so that the VCO output frequency is between 96 and 3441MHz.
pub fn set_plln(&mut self, val: Plln)
pub fn set_plln(&mut self, val: Plln)
PLL frequency multiplication factor N This bit is controlled by software to set the division factor of the fVCO feedback divider (that determines the PLL multiplication ratio) as follows: … … The bitfield can be written only when the PLL is disabled. Caution: The software must set these bits so that the VCO output frequency is between 96 and 3441MHz.
pub const fn pllpen(&self) -> bool
pub const fn pllpen(&self) -> bool
PLLPCLK clock output enable This bit is controlled by software to enable/disable the PLLPCLK clock output of the PLL: Disabling the PLLPCLK clock output, when not used, allows saving power.
pub fn set_pllpen(&mut self, val: bool)
pub fn set_pllpen(&mut self, val: bool)
PLLPCLK clock output enable This bit is controlled by software to enable/disable the PLLPCLK clock output of the PLL: Disabling the PLLPCLK clock output, when not used, allows saving power.
pub const fn pllp(&self) -> Pllp
pub const fn pllp(&self) -> Pllp
PLL VCO division factor P for PLLPCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor P as follows: … The bitfield can be written only when the PLL is disabled. Caution: The software must set this bitfield so as not to exceed 541MHz on this clock.
pub fn set_pllp(&mut self, val: Pllp)
pub fn set_pllp(&mut self, val: Pllp)
PLL VCO division factor P for PLLPCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor P as follows: … The bitfield can be written only when the PLL is disabled. Caution: The software must set this bitfield so as not to exceed 541MHz on this clock.
pub const fn pllqen(&self) -> bool
pub const fn pllqen(&self) -> bool
PLLQCLK clock output enable This bit is controlled by software to enable/disable the PLLQCLK clock output of the PLL: Disabling the PLLQCLK clock output, when not used, allows saving power.
pub fn set_pllqen(&mut self, val: bool)
pub fn set_pllqen(&mut self, val: bool)
PLLQCLK clock output enable This bit is controlled by software to enable/disable the PLLQCLK clock output of the PLL: Disabling the PLLQCLK clock output, when not used, allows saving power.
pub const fn pllq(&self) -> Pllq
pub const fn pllq(&self) -> Pllq
PLL VCO division factor Q for PLLQCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor Q as follows: The bitfield can be written only when the PLL is disabled. Caution: The software must set this bitfield so as not to exceed 541MHz on this clock.
pub fn set_pllq(&mut self, val: Pllq)
pub fn set_pllq(&mut self, val: Pllq)
PLL VCO division factor Q for PLLQCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor Q as follows: The bitfield can be written only when the PLL is disabled. Caution: The software must set this bitfield so as not to exceed 541MHz on this clock.
pub const fn pllren(&self) -> bool
pub const fn pllren(&self) -> bool
PLLRCLK clock output enable This bit is controlled by software to enable/disable the PLLRCLK clock output of the PLL: This bit cannot be written when PLLRCLK output of the PLL is selected for system clock. Disabling the PLLRCLK clock output, when not used, allows saving power.
pub fn set_pllren(&mut self, val: bool)
pub fn set_pllren(&mut self, val: bool)
PLLRCLK clock output enable This bit is controlled by software to enable/disable the PLLRCLK clock output of the PLL: This bit cannot be written when PLLRCLK output of the PLL is selected for system clock. Disabling the PLLRCLK clock output, when not used, allows saving power.
pub const fn pllr(&self) -> Pllr
pub const fn pllr(&self) -> Pllr
PLL VCO division factor R for PLLRCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor R as follows: The bitfield can be written only when the PLL is disabled. The PLLRCLK clock can be selected as system clock. Caution: The software must set this bitfield so as not to exceed 122MHz on this clock.
pub fn set_pllr(&mut self, val: Pllr)
pub fn set_pllr(&mut self, val: Pllr)
PLL VCO division factor R for PLLRCLK clock output This bitfield is controlled by software. It sets the PLL VCO division factor R as follows: The bitfield can be written only when the PLL is disabled. The PLLRCLK clock can be selected as system clock. Caution: The software must set this bitfield so as not to exceed 122MHz on this clock.
Trait Implementations§
impl Copy for Pllcfgr
impl Eq for Pllcfgr
impl StructuralPartialEq for Pllcfgr
Auto Trait Implementations§
impl Freeze for Pllcfgr
impl RefUnwindSafe for Pllcfgr
impl Send for Pllcfgr
impl Sync for Pllcfgr
impl Unpin for Pllcfgr
impl UnwindSafe for Pllcfgr
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
source§unsafe fn clone_to_uninit(&self, dst: *mut T)
unsafe fn clone_to_uninit(&self, dst: *mut T)
clone_to_uninit
)