Struct stm32_metapac::pwr::regs::Scr
#[repr(transparent)]pub struct Scr(pub u32);
Expand description
Power status clear register
Tuple Fields§
§0: u32
Implementations§
§impl Scr
impl Scr
pub const fn cwuf1(&self) -> bool
pub const fn cwuf1(&self) -> bool
Clear wake-up flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register.
pub fn set_cwuf1(&mut self, val: bool)
pub fn set_cwuf1(&mut self, val: bool)
Clear wake-up flag 1 Setting this bit clears the WUF1 flag in the PWR_SR1 register.
pub const fn cwuf2(&self) -> bool
pub const fn cwuf2(&self) -> bool
Clear wake-up flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register.
pub fn set_cwuf2(&mut self, val: bool)
pub fn set_cwuf2(&mut self, val: bool)
Clear wake-up flag 2 Setting this bit clears the WUF2 flag in the PWR_SR1 register.
pub const fn cwuf3(&self) -> bool
pub const fn cwuf3(&self) -> bool
Clear wake-up flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register.
pub fn set_cwuf3(&mut self, val: bool)
pub fn set_cwuf3(&mut self, val: bool)
Clear wake-up flag 3 Setting this bit clears the WUF3 flag in the PWR_SR1 register.
pub const fn cwuf4(&self) -> bool
pub const fn cwuf4(&self) -> bool
Clear wake-up flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register.
pub fn set_cwuf4(&mut self, val: bool)
pub fn set_cwuf4(&mut self, val: bool)
Clear wake-up flag 4 Setting this bit clears the WUF4 flag in the PWR_SR1 register.
pub const fn cwuf5(&self) -> bool
pub const fn cwuf5(&self) -> bool
Clear wake-up flag 5 Setting this bit clears the WUF5 flag in the PWR_SR1 register.
pub fn set_cwuf5(&mut self, val: bool)
pub fn set_cwuf5(&mut self, val: bool)
Clear wake-up flag 5 Setting this bit clears the WUF5 flag in the PWR_SR1 register.
pub const fn cwuf7(&self) -> bool
pub const fn cwuf7(&self) -> bool
Clear wake-up flag 7 Setting this bit clears the WUF7 flag in the PWR_SR1 register.
pub fn set_cwuf7(&mut self, val: bool)
pub fn set_cwuf7(&mut self, val: bool)
Clear wake-up flag 7 Setting this bit clears the WUF7 flag in the PWR_SR1 register.