Struct stm32_metapac::syscfg::regs::Cfgr2

#[repr(transparent)]
pub struct Cfgr2(pub u32);

SYSCFG configuration register 2

Tuple Fields

0: u32

Implementations

impl Cfgr2

pub const fn ccl(&self) -> bool

Cortex1<Default 1 Font>-M0+ LOCKUP bit enable bit This bit is set by software and cleared by a system reset. It can be use to enable and lock the connection of Cortex1<Default 1 Font>-M0+ LOCKUP (Hardfault) output to TIM1/15/16 Break input.

pub fn set_ccl(&mut self, val: bool)

Cortex1<Default 1 Font>-M0+ LOCKUP bit enable bit This bit is set by software and cleared by a system reset. It can be use to enable and lock the connection of Cortex1<Default 1 Font>-M0+ LOCKUP (Hardfault) output to TIM1/15/16 Break input.

pub const fn spl(&self) -> bool

SRAM1 parity lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM1 parity error signal connection to TIM1/15/16 Break input.

pub fn set_spl(&mut self, val: bool)

SRAM1 parity lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM1 parity error signal connection to TIM1/15/16 Break input.

pub const fn pvdl(&self) -> bool

PVD lock enable bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM1/15/16 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register.

pub fn set_pvdl(&mut self, val: bool)

PVD lock enable bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the PVD connection to TIM1/15/16 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR register.

pub const fn eccl(&self) -> bool

ECC error lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the flash ECC 2-bit error detection signal connection to TIM1/15/16 Break input.

pub fn set_eccl(&mut self, val: bool)

ECC error lock bit This bit is set by software and cleared by a system reset. It can be used to enable and lock the flash ECC 2-bit error detection signal connection to TIM1/15/16 Break input.

pub const fn bkpl(&self) -> bool

Backup SRAM2 parity lock This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/15/16 Break input.

pub fn set_bkpl(&mut self, val: bool)

Backup SRAM2 parity lock This bit is set by software and cleared by a system reset. It can be used to enable and lock the SRAM2 parity error signal connection to TIM1/15/16 Break input.

pub const fn bkpf(&self) -> bool

Backup SRAM2 parity error flag This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing 1.

pub fn set_bkpf(&mut self, val: bool)

Backup SRAM2 parity error flag This bit is set by hardware when an SRAM2 parity error is detected. It is cleared by software by writing 1.

pub const fn spf(&self) -> bool

SRAM1 parity error flag This bit is set by hardware when an SRAM1 parity error is detected. It is cleared by software by writing 1.

pub fn set_spf(&mut self, val: bool)

SRAM1 parity error flag This bit is set by hardware when an SRAM1 parity error is detected. It is cleared by software by writing 1.

Trait Implementations

impl Clone for Cfgr2

fn clone(&self) -> Cfgr2

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Cfgr2

fn default() -> Cfgr2

Returns the “default value” for a type.

impl PartialEq for Cfgr2

fn eq(&self, other: &Cfgr2) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Cfgr2

impl Eq for Cfgr2

impl StructuralPartialEq for Cfgr2