Struct Apb1lfzr 

#[repr(transparent)]
pub struct Apb1lfzr(pub u32);

DBGMCU APB1L peripheral freeze register.

Tuple Fields

0: u32

Implementations

impl Apb1lfzr

pub const fn dbg_tim2_stop(&self) -> bool

None 0: normal operation. TIM2 continues to operate while CPU is in debug mode. 1: stop in debug. TIM2 is frozen while CPU is in debug mode.

pub fn set_dbg_tim2_stop(&mut self, val: bool)

None 0: normal operation. TIM2 continues to operate while CPU is in debug mode. 1: stop in debug. TIM2 is frozen while CPU is in debug mode.

pub const fn dbg_tim3_stop(&self) -> bool

None 0: normal operation. TIM3 continues to operate while CPU is in debug mode. 1: stop in debug. TIM3 is frozen while CPU is in debug mode.

pub fn set_dbg_tim3_stop(&mut self, val: bool)

None 0: normal operation. TIM3 continues to operate while CPU is in debug mode. 1: stop in debug. TIM3 is frozen while CPU is in debug mode.

pub const fn dbg_tim4_stop(&self) -> bool

None 0: normal operation. TIM4 continues to operate while CPU is in debug mode. 1: stop in debug. TIM4 is frozen while CPU is in debug mode.

pub fn set_dbg_tim4_stop(&mut self, val: bool)

None 0: normal operation. TIM4 continues to operate while CPU is in debug mode. 1: stop in debug. TIM4 is frozen while CPU is in debug mode.

pub const fn dbg_tim6_stop(&self) -> bool

None 0: normal operation. TIM6 continues to operate while CPU is in debug mode. 1: stop in debug. TIM6 is frozen while CPU is in debug mode.

pub fn set_dbg_tim6_stop(&mut self, val: bool)

None 0: normal operation. TIM6 continues to operate while CPU is in debug mode. 1: stop in debug. TIM6 is frozen while CPU is in debug mode.

pub const fn dbg_tim7_stop(&self) -> bool

None 0: normal operation. TIM7 continues to operate while CPU is in debug mode. 1: stop in debug. TIM7 is frozen while CPU is in debug mode.

pub fn set_dbg_tim7_stop(&mut self, val: bool)

None 0: normal operation. TIM7 continues to operate while CPU is in debug mode. 1: stop in debug. TIM7 is frozen while CPU is in debug mode.

pub const fn dbg_wwdg_stop(&self) -> bool

None 0: normal operation. WWDG continues to operate while CPU is in debug mode. 1: stop in debug. WWDG is frozen while CPU is in debug mode.

pub fn set_dbg_wwdg_stop(&mut self, val: bool)

None 0: normal operation. WWDG continues to operate while CPU is in debug mode. 1: stop in debug. WWDG is frozen while CPU is in debug mode.

pub const fn dbg_iwdg_stop(&self) -> bool

None 0: normal operation. IWDG continues to operate while CPU is in debug mode. 1: stop in debug. IWDG is frozen while CPU is in debug mode.

pub fn set_dbg_iwdg_stop(&mut self, val: bool)

None 0: normal operation. IWDG continues to operate while CPU is in debug mode. 1: stop in debug. IWDG is frozen while CPU is in debug mode.

pub const fn dbg_i2c1_stop(&self) -> bool

None 0: normal operation. I2C1 SMBUS timeout continues to operate while CPU is in debug mode. 1: stop in debug. I2C1 SMBUS timeout is frozen while CPU is in debug mode.

pub fn set_dbg_i2c1_stop(&mut self, val: bool)

None 0: normal operation. I2C1 SMBUS timeout continues to operate while CPU is in debug mode. 1: stop in debug. I2C1 SMBUS timeout is frozen while CPU is in debug mode.

pub const fn dbg_i2c2_stop(&self) -> bool

None 0: normal operation. I2C2 SMBUS timeout continues to operate while CPU is in debug mode. 1: stop in debug. I2C2 SMBUS timeout is frozen while CPU is in debug mode.

pub fn set_dbg_i2c2_stop(&mut self, val: bool)

None 0: normal operation. I2C2 SMBUS timeout continues to operate while CPU is in debug mode. 1: stop in debug. I2C2 SMBUS timeout is frozen while CPU is in debug mode.

pub const fn dbg_i3c1_stop(&self) -> bool

None 0: normal operation. I3C1 timeout continues to operate while CPU is in debug mode. 1: stop in debug. I3C1 timeout is frozen while CPU is in debug mode.

pub fn set_dbg_i3c1_stop(&mut self, val: bool)

None 0: normal operation. I3C1 timeout continues to operate while CPU is in debug mode. 1: stop in debug. I3C1 timeout is frozen while CPU is in debug mode.

pub const fn dbg_rtc_stop(&self) -> bool

None 0: normal operation. RTC continues to operate while CPU is in debug mode. 1: stop in debug. RTC is frozen while CPU is in debug mode.

pub fn set_dbg_rtc_stop(&mut self, val: bool)

None 0: normal operation. RTC continues to operate while CPU is in debug mode. 1: stop in debug. RTC is frozen while CPU is in debug mode.

Trait Implementations

impl Clone for Apb1lfzr

fn clone(&self) -> Apb1lfzr

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Apb1lfzr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Apb1lfzr

fn default() -> Apb1lfzr

Returns the “default value” for a type.

impl PartialEq for Apb1lfzr

fn eq(&self, other: &Apb1lfzr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Apb1lfzr

impl Eq for Apb1lfzr

impl StructuralPartialEq for Apb1lfzr