Struct Apb2fzr
#[repr(transparent)]pub struct Apb2fzr(pub u32);Expand description
DBGMCU APB2 peripheral freeze register.
Tuple Fields§
§0: u32Implementations§
§impl Apb2fzr
impl Apb2fzr
pub const fn dbg_tim1_stop(&self) -> bool
pub const fn dbg_tim1_stop(&self) -> bool
None 0: normal operation. TIM1 continues to operate while CPU is in debug mode. 1: stop in debug. TIM1 is frozen while CPU is in debug mode.
pub fn set_dbg_tim1_stop(&mut self, val: bool)
pub fn set_dbg_tim1_stop(&mut self, val: bool)
None 0: normal operation. TIM1 continues to operate while CPU is in debug mode. 1: stop in debug. TIM1 is frozen while CPU is in debug mode.
pub const fn dbg_tim15_stop(&self) -> bool
pub const fn dbg_tim15_stop(&self) -> bool
None 0: normal operation. TIM15 continues to operate while CPU is in debug mode. 1: stop in debug. TIM15 is frozen while CPU is in debug mode.
pub fn set_dbg_tim15_stop(&mut self, val: bool)
pub fn set_dbg_tim15_stop(&mut self, val: bool)
None 0: normal operation. TIM15 continues to operate while CPU is in debug mode. 1: stop in debug. TIM15 is frozen while CPU is in debug mode.
pub const fn dbg_tim16_stop(&self) -> bool
pub const fn dbg_tim16_stop(&self) -> bool
None 0: normal operation. TIM16 continues to operate while CPU is in debug mode. 1: stop in debug. TIM16 is frozen while CPU is in debug mode.
pub fn set_dbg_tim16_stop(&mut self, val: bool)
pub fn set_dbg_tim16_stop(&mut self, val: bool)
None 0: normal operation. TIM16 continues to operate while CPU is in debug mode. 1: stop in debug. TIM16 is frozen while CPU is in debug mode.
pub const fn dbg_tim17_stop(&self) -> bool
pub const fn dbg_tim17_stop(&self) -> bool
None 0: normal operation. TIM17 continues to operate while CPU is in debug mode. 1: stop in debug. TIM17 is frozen while CPU is in debug mode.
pub fn set_dbg_tim17_stop(&mut self, val: bool)
pub fn set_dbg_tim17_stop(&mut self, val: bool)
None 0: normal operation. TIM17 continues to operate while CPU is in debug mode. 1: stop in debug. TIM17 is frozen while CPU is in debug mode.
pub const fn dbg_i3c2_stop(&self) -> bool
pub const fn dbg_i3c2_stop(&self) -> bool
None 0: normal operation. I3C2 timeout continues to operate while CPU is in debug mode. 1: stop in debug. I3C2 timeout is frozen while CPU is in debug mode.
pub fn set_dbg_i3c2_stop(&mut self, val: bool)
pub fn set_dbg_i3c2_stop(&mut self, val: bool)
None 0: normal operation. I3C2 timeout continues to operate while CPU is in debug mode. 1: stop in debug. I3C2 timeout is frozen while CPU is in debug mode.