Struct Vosr

#[repr(transparent)]
pub struct Vosr(pub u32);

Expand description

PWR voltage scaling register.

Tuple Fields§

§0: u32

Implementations§

§

impl Vosr

pub const fn r1en(&self) -> bool

This field is protected against non-secure access when SYSCLKSEC=1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC=1 in RCC_SECCFGR and SPRIV=1 in PRIVCFGR, or when SYSCLKSEC=0 and NSPRIV=1. 0: Voltage scaling range 1 disabled 1: Voltage scaling range 1 enabled Note: R1EN and R2EN must be at opposite value. Any attempt to write R1EN and R2EN to same value is ignored. Modifying R1EN and R2EN is possible only when current range is ready (R1RDY=R1EN and R2RDY=R2EN).

pub fn set_r1en(&mut self, val: bool)

This field is protected against non-secure access when SYSCLKSEC=1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC=1 in RCC_SECCFGR and SPRIV=1 in PRIVCFGR, or when SYSCLKSEC=0 and NSPRIV=1. 0: Voltage scaling range 1 disabled 1: Voltage scaling range 1 enabled Note: R1EN and R2EN must be at opposite value. Any attempt to write R1EN and R2EN to same value is ignored. Modifying R1EN and R2EN is possible only when current range is ready (R1RDY=R1EN and R2RDY=R2EN).

pub const fn r2en(&self) -> bool

This field is protected against non-secure access when SYSCLKSEC=1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC=1 in RCC_SECCFGR and SPRIV=1 in PRIVCFGR, or when SYSCLKSEC=0 and NSPRIV=1. 0: Voltage scaling range 2 disabled 1: Voltage scaling range 2 enabled Note: R1EN and R2EN must be at opposite value. Any attempt to write R1EN and R2EN to same value is ignored. Modifying R1EN and R2EN is possible only when current range is ready (R1RDY=R1EN and R2RDY=R2EN).

pub fn set_r2en(&mut self, val: bool)

This field is protected against non-secure access when SYSCLKSEC=1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC=1 in RCC_SECCFGR and SPRIV=1 in PRIVCFGR, or when SYSCLKSEC=0 and NSPRIV=1. 0: Voltage scaling range 2 disabled 1: Voltage scaling range 2 enabled Note: R1EN and R2EN must be at opposite value. Any attempt to write R1EN and R2EN to same value is ignored. Modifying R1EN and R2EN is possible only when current range is ready (R1RDY=R1EN and R2RDY=R2EN).

pub const fn boosten(&self) -> bool

This bit is protected against non-secure access when SYSCLKSEC=1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC=1 in RCC_SECCFGR and SPRIV=1 in PRIVCFGR, or when SYSCLKSEC=0 and NSPRIV=1. This bit must be set in Range 1, and before increasing the system clock frequency above 24 MHz in Range 2. The booster clock must be configured before setting this bit, and must not be disabled as long as the booster is enabled. 0: Booster disabled 1: Booster enabled.

pub fn set_boosten(&mut self, val: bool)

This bit is protected against non-secure access when SYSCLKSEC=1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC=1 in RCC_SECCFGR and SPRIV=1 in PRIVCFGR, or when SYSCLKSEC=0 and NSPRIV=1. This bit must be set in Range 1, and before increasing the system clock frequency above 24 MHz in Range 2. The booster clock must be configured before setting this bit, and must not be disabled as long as the booster is enabled. 0: Booster disabled 1: Booster enabled.

pub const fn r1rdy(&self) -> bool

None 0: Range 1 not ready: voltage level less than VOS range 1 level 1: Range 1 ready: voltage level greater or equal VOS range 1 level Note: R1RDY and R2RDY cannot be set at the same time.

pub fn set_r1rdy(&mut self, val: bool)

None 0: Range 1 not ready: voltage level less than VOS range 1 level 1: Range 1 ready: voltage level greater or equal VOS range 1 level Note: R1RDY and R2RDY cannot be set at the same time.

pub const fn r2rdy(&self) -> bool

None 0: Range 2 not ready: voltage level less than VOS range 2 level 1: Range 2 ready: voltage level greater or equal VOS range 2 level Note: R1RDY and R2RDY cannot be set at the same time.

pub fn set_r2rdy(&mut self, val: bool)

None 0: Range 2 not ready: voltage level less than VOS range 2 level 1: Range 2 ready: voltage level greater or equal VOS range 2 level Note: R1RDY and R2RDY cannot be set at the same time.

pub const fn boostrdy(&self) -> bool

This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 24 MHz only after this bit is set. Disabling the booster clock when the booster is ready is forbidden. 0: Power booster not ready 1: Power booster ready.

pub fn set_boostrdy(&mut self, val: bool)

This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 24 MHz only after this bit is set. Disabling the booster clock when the booster is ready is forbidden. 0: Power booster not ready 1: Power booster ready.