Struct Cr 

#[repr(transparent)]
pub struct Cr(pub u32);

DBGMCU configuration register.

Tuple Fields

0: u32

Implementations

impl Cr

pub const fn dbg_stop(&self) -> bool

All clocks are disabled automatically in Stop mode. All active clocks and oscillators continue to run during Stop mode, allowing full debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state. 0: normal operation 1: automatic clock stop disabled.

pub fn set_dbg_stop(&mut self, val: bool)

All clocks are disabled automatically in Stop mode. All active clocks and oscillators continue to run during Stop mode, allowing full debug capability. On exit from Stop mode, the clock settings are set to the Stop mode exit state. 0: normal operation 1: automatic clock stop disabled.

pub const fn dbg_standby(&self) -> bool

All clocks are disabled and the core powered down automatically in Standby mode. All active clocks and oscillators continue to run during Standby mode, and the core supply is maintained, allowing full debug capability. On exit from Standby mode, a system reset is performed. 0: normal operation 1: automatic clock stop/power down disabled.

pub fn set_dbg_standby(&mut self, val: bool)

All clocks are disabled and the core powered down automatically in Standby mode. All active clocks and oscillators continue to run during Standby mode, and the core supply is maintained, allowing full debug capability. On exit from Standby mode, a system reset is performed. 0: normal operation 1: automatic clock stop/power down disabled.

pub const fn trace_ioen(&self) -> bool

None 0: disabled-trace pins not assigned 1: enabled-trace pins assigned according to the value of TRACE_MODE field.

pub fn set_trace_ioen(&mut self, val: bool)

None 0: disabled-trace pins not assigned 1: enabled-trace pins assigned according to the value of TRACE_MODE field.

pub const fn trace_en(&self) -> bool

This bit enables the trace port clock, TRACECK. 0: disabled 1: enabled.

pub fn set_trace_en(&mut self, val: bool)

This bit enables the trace port clock, TRACECK. 0: disabled 1: enabled.

pub const fn trace_mode(&self) -> u8

None 0x0: trace pins assigned for asynchronous mode (TRACESWO) 0x1: trace pins assigned for synchronous mode with a port width of 1 (TRACECK, TRACED0) 0x2: trace pins assigned for synchronous mode with a port width of 2 ((TRACECK, TRACED0-1) 0x3: trace pins assigned for synchronous mode with a port width of 4 ((TRACECK, TRACED0-3).

pub fn set_trace_mode(&mut self, val: u8)

None 0x0: trace pins assigned for asynchronous mode (TRACESWO) 0x1: trace pins assigned for synchronous mode with a port width of 1 (TRACECK, TRACED0) 0x2: trace pins assigned for synchronous mode with a port width of 2 ((TRACECK, TRACED0-1) 0x3: trace pins assigned for synchronous mode with a port width of 4 ((TRACECK, TRACED0-3).

Trait Implementations

impl Clone for Cr

fn clone(&self) -> Cr

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Cr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Cr

fn default() -> Cr

Returns the “default value” for a type.

impl PartialEq for Cr

fn eq(&self, other: &Cr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Cr

impl Eq for Cr

impl StructuralPartialEq for Cr