Module vals 

Enums

Acicn

Auxiliary CIC order selection.

Acqmod

Digital filter trigger mode.

Bssel

Bitstream selection. This bitfield is set and cleared by software. It is used to select the bitstream to be used by the DFLT0.

Cckdir

CCK1 direction. This bit is set and reset by software. It is used to control the direction of the ADF_CCK1 pin.

Cckdiv

Divider to control the CCK clock. This bit is set and reset by software. It is used to control the frequency of the bitstream clock on the CCK pin.

Cicmod

CIC filter mode selection.

Ckgmod

Clock generator mode. This bit is set and reset by software. It is used to define the way the clock generator is enabled. This bit must not be changed if the filter is enabled (DFTEN = 1).

Datsrc

Source data for the digital filter.

Hpfc

High-pass filter cut-off frequency. This bitfield is set and cleared by software. it is used to select the cut-off frequency of the high-pass filter. F PCM represents the sampling frequency at HPF input.

Intdiv

Integrator output division.

Rsfltd

Reshaper filter decimation ratio. This bitfield is set and cleared by software. It is used to select the decimation ratio of the reshaper filter.

Rxfifo

RXFIFO threshold selection. This bitfield is set and cleared by software. It is used to select the RXFIFO threshold.

Scksrc

Serial clock source. This bitfield is set and cleared by software. It is used to select the clock source of the serial interface.

Sitfmod

Serial interface mode. This bitfield is set and cleared by software. It is used to select the serial interface mode.

Snpsfmt

Snapshot data format.

Thinb

Out-of-limit threshold band mode.

Trgsens

CKGEN trigger sensitivity selection. This bit is set and cleared by software. It is used to select the trigger sensitivity of the trigger signals. This bit is not significant if the CKGMOD = 0.

Trgsrc

Digital filter trigger signal selection.