Struct stm32_metapac::rcc::regs::Plldivr
#[repr(transparent)]pub struct Plldivr(pub u32);
Expand description
RCC PLL1 dividers register
Tuple Fields§
§0: u32
Implementations§
§impl Plldivr
impl Plldivr
pub const fn plln(&self) -> Plln
pub const fn plln(&self) -> Plln
Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). … … Others: reserved VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with: PLL1N between 4 and 512 input frequency Fref1_ck between 4 and 16 MHz
pub fn set_plln(&mut self, val: Plln)
pub fn set_plln(&mut self, val: Plln)
Multiplication factor for PLL1 VCO Set and reset by software to control the multiplication factor of the VCO. These bits can be written only when the PLL is disabled (PLL1ON = 0 and PLL1RDY = 0). … … Others: reserved VCO output frequency = Fref1_ck x PLL1N, when fractional value 0 has been loaded into PLL1FRACN, with: PLL1N between 4 and 512 input frequency Fref1_ck between 4 and 16 MHz
pub const fn pllp(&self) -> Plldiv
pub const fn pllp(&self) -> Plldiv
PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. …
pub fn set_pllp(&mut self, val: Plldiv)
pub fn set_pllp(&mut self, val: Plldiv)
PLL1 DIVP division factor Set and reset by software to control the frequency of the pll1_p_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). Note that odd division factors are not allowed. …
pub const fn pllq(&self) -> Plldiv
pub const fn pllq(&self) -> Plldiv
PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). …
pub fn set_pllq(&mut self, val: Plldiv)
pub fn set_pllq(&mut self, val: Plldiv)
PLL1 DIVQ division factor Set and reset by software to control the frequency of the pll1_q_ck clock. These bits can be written only when the PLL1 is disabled (PLL1ON = 0 and PLL1RDY = 0). …
Trait Implementations§
impl Copy for Plldivr
impl Eq for Plldivr
impl StructuralPartialEq for Plldivr
Auto Trait Implementations§
impl Freeze for Plldivr
impl RefUnwindSafe for Plldivr
impl Send for Plldivr
impl Sync for Plldivr
impl Unpin for Plldivr
impl UnwindSafe for Plldivr
Blanket Implementations§
source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
source§impl<T> CloneToUninit for Twhere
T: Clone,
impl<T> CloneToUninit for Twhere
T: Clone,
source§unsafe fn clone_to_uninit(&self, dst: *mut T)
unsafe fn clone_to_uninit(&self, dst: *mut T)
clone_to_uninit
)