Struct stm32_metapac::can::regs::Ecr
#[repr(transparent)]pub struct Ecr(pub u32);
Expand description
FDCAN error counter register
Tuple Fields§
§0: u32
Implementations§
§impl Ecr
impl Ecr
pub const fn tec(&self) -> u8
pub const fn tec(&self) -> u8
Transmit error counter. Actual state of the transmit error counter, values between 0 and 255. When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented
pub fn set_tec(&mut self, val: u8)
pub fn set_tec(&mut self, val: u8)
Transmit error counter. Actual state of the transmit error counter, values between 0 and 255. When CCCR.ASM is set, the CAN protocol controller does not increment TEC and REC when a CAN protocol error is detected, but CEL is still incremented
pub const fn rec(&self) -> u8
pub const fn rec(&self) -> u8
Receive error counter. Actual state of the receive error counter, values between 0 and 127
pub fn set_rec(&mut self, val: u8)
pub fn set_rec(&mut self, val: u8)
Receive error counter. Actual state of the receive error counter, values between 0 and 127
pub const fn cel(&self) -> u8
pub const fn cel(&self) -> u8
CAN error logging. The counter is incremented each time when a CAN protocol error causes the transmit error counter or the receive error counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR[ELO]. Access type is RX: reset on read.
pub fn set_cel(&mut self, val: u8)
pub fn set_cel(&mut self, val: u8)
CAN error logging. The counter is incremented each time when a CAN protocol error causes the transmit error counter or the receive error counter to be incremented. It is reset by read access to CEL. The counter stops at 0xFF; the next increment of TEC or REC sets interrupt flag IR[ELO]. Access type is RX: reset on read.