Struct stm32_metapac::lpdma::regs::ChTr1
#[repr(transparent)]pub struct ChTr1(pub u32);
Expand description
LPDMA channel 8 transfer register 1
Tuple Fields§
§0: u32
Implementations§
§impl ChTr1
impl ChTr1
pub const fn sdw(&self) -> Dw
pub const fn sdw(&self) -> Dw
binary logarithm of the source data width of a burst in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (CH[x].BR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address CH[x].SAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.
pub fn set_sdw(&mut self, val: Dw)
pub fn set_sdw(&mut self, val: Dw)
binary logarithm of the source data width of a burst in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and no transfer is issued. A source block size must be a multiple of the source data width (CH[x].BR1.BNDT[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and no transfer is issued. A source single transfer must have an aligned address with its data width (start address CH[x].SAR[2:0] versus SDW_LOG2[1:0]). Otherwise, a user setting error is reported and none transfer is issued.
pub const fn sinc(&self) -> bool
pub const fn sinc(&self) -> bool
source incrementing burst. The source address, pointed by CH[x].SAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer.
pub fn set_sinc(&mut self, val: bool)
pub fn set_sinc(&mut self, val: bool)
source incrementing burst. The source address, pointed by CH[x].SAR, is kept constant after a burst beat/single transfer or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer.
pub const fn pam(&self) -> Pam
pub const fn pam(&self) -> Pam
padding/alignment mode. If DDW[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note:
pub fn set_pam(&mut self, val: Pam)
pub fn set_pam(&mut self, val: Pam)
padding/alignment mode. If DDW[1:0] = SDW_LOG2[1:0]: if the data width of a burst destination transfer is equal to the data width of a burst source transfer, these bits are ignored. Else: - Case 1: If destination data width > source data width. 1x: successive source data are FIFO queued and packed at the destination data width, in a left (LSB) to right (MSB) order (named little endian), before a destination transfer. - Case 2: If destination data width < source data width. 1x: source data is FIFO queued and unpacked at the destination data width, to be transferred in a left (LSB) to right (MSB) order (named little endian) to the destination. Note:
pub const fn ssec(&self) -> bool
pub const fn ssec(&self) -> bool
security attribute of the LPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer from the source is non-secure.
pub fn set_ssec(&mut self, val: bool)
pub fn set_ssec(&mut self, val: bool)
security attribute of the LPDMA transfer from the source. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx =1 . A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this SSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer from the source is non-secure.
pub const fn ddw(&self) -> Dw
pub const fn ddw(&self) -> Dw
binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued.
pub fn set_ddw(&mut self, val: Dw)
pub fn set_ddw(&mut self, val: Dw)
binary logarithm of the destination data width of a burst, in bytes. Note: Setting a 8-byte data width causes a user setting error to be reported and none transfer is issued. A destination burst transfer must have an aligned address with its data width (start address CH[x].DAR[2:0] and address offset CH[x].TR3.DAO[2:0], versus DDW[1:0]). Otherwise a user setting error is reported and no transfer is issued.
pub const fn dinc(&self) -> bool
pub const fn dinc(&self) -> bool
destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer.
pub fn set_dinc(&mut self, val: bool)
pub fn set_dinc(&mut self, val: bool)
destination incrementing burst. The destination address, pointed by CH[x].DAR, is kept constant after a burst beat/single transfer, or is incremented by the offset value corresponding to a contiguous data after a burst beat/single transfer.
pub const fn dsec(&self) -> bool
pub const fn dsec(&self) -> bool
security attribute of the LPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer to the destination is non-secure.
pub fn set_dsec(&mut self, val: bool)
pub fn set_dsec(&mut self, val: bool)
security attribute of the LPDMA transfer to the destination. If SECCFGR.SECx = 1 and the access is secure: This is a secure register bit. This bit can only be read by a secure software. This bit must be written by a secure software when SECCFGR.SECx = 1. A secure write is ignored when SECCFGR.SECx = 0. When SECCFGR.SECx is de-asserted, this DSEC bit is also de-asserted by hardware (on a secure reconfiguration of the channel as non-secure), and the LPDMA transfer to the destination is non-secure.