Struct stm32_metapac::hspi::regs::Cr

#[repr(transparent)]
pub struct Cr(pub u32);

HSPI control register.

Tuple Fields

0: u32

Implementations

impl Cr

pub const fn en(&self) -> bool

Enable This bit enables the HSPI. Note: The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. In case this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active.

pub fn set_en(&mut self, val: bool)

Enable This bit enables the HSPI. Note: The DMA request can be aborted without having received the ACK in case this EN bit is cleared during the operation. In case this bit is set to 0 during a DMA transfer, the REQ signal to DMA returns to inactive state without waiting for the ACK signal from DMA to be active.

pub const fn abort(&self) -> bool

Abort request This bit aborts the on-going command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. Note: This bit is always read as 0.

pub fn set_abort(&mut self, val: bool)

Abort request This bit aborts the on-going command sequence. It is automatically reset once the abort is completed. This bit stops the current transfer. Note: This bit is always read as 0.

pub const fn dmaen(&self) -> bool

DMA enable In Indirect mode, the DMA can be used to input or output data via DR. DMA transfers are initiated when FTF is set. Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write this bit during DMA operation.

pub fn set_dmaen(&mut self, val: bool)

DMA enable In Indirect mode, the DMA can be used to input or output data via DR. DMA transfers are initiated when FTF is set. Note: Resetting the DMAEN bit while a DMA transfer is ongoing, breaks the handshake with the DMA. Do not write this bit during DMA operation.

pub const fn tcen(&self) -> bool

Timeout counter enable This bit is valid only when the Memory-mapped mode (FMODE[1:0] = 11) is selected. This bit enables the timeout counter.

pub fn set_tcen(&mut self, val: bool)

Timeout counter enable This bit is valid only when the Memory-mapped mode (FMODE[1:0] = 11) is selected. This bit enables the timeout counter.

pub const fn dmm(&self) -> bool

Dual-memory mode This bit activates the Dual-memory mode, where two external devices are used simultaneously to double the throughput and the capacity.

pub fn set_dmm(&mut self, val: bool)

Dual-memory mode This bit activates the Dual-memory mode, where two external devices are used simultaneously to double the throughput and the capacity.

pub const fn fsel(&self) -> bool

Memory select This bit is the mirror of bit 30. Refer to the description of MSEL[1:0] above. This bit is set when 1 is written in bit 30 or bit 7. When this bit is set, both b30 and b7 are read as 1. This bit is reset when bit 30 and bit7 are set to 0. When this bit is reset, both bit 30 and bit7 are read as 0.

pub fn set_fsel(&mut self, val: bool)

Memory select This bit is the mirror of bit 30. Refer to the description of MSEL[1:0] above. This bit is set when 1 is written in bit 30 or bit 7. When this bit is set, both b30 and b7 are read as 1. This bit is reset when bit 30 and bit7 are set to 0. When this bit is reset, both bit 30 and bit7 are read as 0.

pub const fn fthres(&self) -> u8

FIFO threshold level This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in SR, to be set. … Note: If DMAEN├é┬á=├é┬á1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[5:0] value.

pub fn set_fthres(&mut self, val: u8)

FIFO threshold level This field defines, in Indirect mode, the threshold number of bytes in the FIFO that causes the FIFO threshold flag FTF in SR, to be set. … Note: If DMAEN├é┬á=├é┬á1, the DMA controller for the corresponding channel must be disabled before changing the FTHRES[5:0] value.

pub const fn teie(&self) -> bool

Transfer error interrupt enable This bit enables the transfer error interrupt.

pub fn set_teie(&mut self, val: bool)

Transfer error interrupt enable This bit enables the transfer error interrupt.

pub const fn tcie(&self) -> bool

Transfer complete interrupt enable This bit enables the transfer complete interrupt.

pub fn set_tcie(&mut self, val: bool)

Transfer complete interrupt enable This bit enables the transfer complete interrupt.

pub const fn ftie(&self) -> bool

FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt.

pub fn set_ftie(&mut self, val: bool)

FIFO threshold interrupt enable This bit enables the FIFO threshold interrupt.

pub const fn smie(&self) -> bool

Status match interrupt enable This bit enables the status match interrupt.

pub fn set_smie(&mut self, val: bool)

Status match interrupt enable This bit enables the status match interrupt.

pub const fn toie(&self) -> bool

Timeout interrupt enable This bit enables the timeout interrupt.

pub fn set_toie(&mut self, val: bool)

Timeout interrupt enable This bit enables the timeout interrupt.

pub const fn apms(&self) -> bool

Automatic-polling mode stop This bit determines if the automatic polling is stopped after a match.

pub fn set_apms(&mut self, val: bool)

Automatic-polling mode stop This bit determines if the automatic polling is stopped after a match.

pub const fn pmm(&self) -> bool

Polling match mode This bit indicates which method must be used to determine a match during the Automatic-polling mode.

pub fn set_pmm(&mut self, val: bool)

Polling match mode This bit indicates which method must be used to determine a match during the Automatic-polling mode.

pub const fn fmode(&self) -> u8

Functional mode This field defines the HSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state.

pub fn set_fmode(&mut self, val: u8)

Functional mode This field defines the HSPI functional mode of operation. If DMAEN = 1 already, then the DMA controller for the corresponding channel must be disabled before changing the FMODE[1:0] value. If FMODE[1:0] and FTHRES[4:0] are wrongly updated while DMAEN = 1, the DMA request signal automatically goes to inactive state.

pub const fn msel(&self) -> u8

Flash select These bits select the memory to be addressed in Single, Dual, Quad or Octal mode in single├ó€‘memory configuration (when DMM = 0). - when in Quad mode: - when in Octal mode or Dual-quad mode: 0x: data exchanged over IO[7:0] 1x: data exchanged over IO[15:8] These bits are ignored when in dual-octal configuration (data on 8 bits and DMM├é┬á=├é┬á1) or 16├ó€‘bit configuration (data exchanged over IO[15:0]).

pub fn set_msel(&mut self, val: u8)

Flash select These bits select the memory to be addressed in Single, Dual, Quad or Octal mode in single├ó€‘memory configuration (when DMM = 0). - when in Quad mode: - when in Octal mode or Dual-quad mode: 0x: data exchanged over IO[7:0] 1x: data exchanged over IO[15:8] These bits are ignored when in dual-octal configuration (data on 8 bits and DMM├é┬á=├é┬á1) or 16├ó€‘bit configuration (data exchanged over IO[15:0]).

Trait Implementations

impl Clone for Cr

fn clone(&self) -> Cr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Cr

fn default() -> Cr

Returns the “default value” for a type.

impl PartialEq for Cr

fn eq(&self, other: &Cr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Cr

impl Eq for Cr

impl StructuralPartialEq for Cr