stm32-metapac

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stm32u5a5rj

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Module stm32_metapac::otg::regs

Structsยง

  • ADP (Attach Detection Protocol) Control Register
  • Core ID register
  • Device all endpoints interrupt register
  • All endpoints interrupt mask register
  • Device configuration register
  • Device control register
  • Device endpoint control register
  • Device IN endpoint FIFO empty interrupt mask register
  • Device endpoint interrupt register
  • Device IN endpoint common interrupt mask register
  • Device endpoint transfer size register
  • Device endpoint control register
  • Device endpoint interrupt register
  • Device OUT endpoint common interrupt mask register
  • Device OUT endpoint transfer size register
  • Device status register
  • Device IN endpoint transmit FIFO status register
  • Device VBUS discharge time register
  • Device VBUS pulsing time register
  • FIFO register
  • FIFO size register
  • AHB configuration register
  • General core configuration register
  • General core configuration register
  • OTG general core configuration register.
  • I2C access register
  • Interrupt mask register
  • Core interrupt register
  • Core LPM configuration register
  • Control and status register
  • Interrupt register
  • Reset register
  • Receive FIFO size register
  • Status read and pop register
  • USB configuration register
  • Host all channels interrupt register
  • Host all channels interrupt mask register
  • Host channel characteristics register
  • Host channel DMA config register
  • Host configuration register
  • Host channel interrupt register
  • Host channel mask register
  • Host channel transfer size register
  • Host frame interval register
  • Host frame number/frame time remaining register
  • Non-periodic transmit FIFO/queue status register
  • Host port control and status register
  • Periodic transmit FIFO/queue status register
  • Power and clock gating control register