Struct stm32_metapac::gpdma::regs::ChCr

#[repr(transparent)]
pub struct ChCr(pub u32);

Expand description

GPDMA channel 11 control register

Tuple Fields§

§0: u32

Implementations§

§

impl ChCr

pub const fn en(&self) -> bool

enable. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored.

pub fn set_en(&mut self, val: bool)

enable. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 0. Else: this bit is de-asserted by hardware when there is a transfer error (master bus error or user setting error) or when there is a channel transfer complete (channel ready to be configured, e.g. if LSM=1 at the end of a single execution of the LLI). Else, this bit can be asserted by software. Writing 0 into this EN bit is ignored.

pub const fn reset(&self) -> bool

reset. This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (CH[x].SR.SUSPF = 1 and CH[x].SR.IDLEF = CH[x].CR.EN = 1). - channel in disabled state (CH[x].SR.IDLEF = 1 and CH[x].CR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (CH[x].BR1, CH[x].SAR and CH[x].DAR) before enabling again the channel (see the programming sequence in ).

pub fn set_reset(&mut self, val: bool)

reset. This bit is write only. Writing 0 has no impact. Writing 1 implies the reset of the following: the FIFO, the channel internal state, SUSP and EN bits (whatever is written receptively in bit 2 and bit 0). The reset is effective when the channel is in steady state, meaning one of the following: - active channel in suspended state (CH[x].SR.SUSPF = 1 and CH[x].SR.IDLEF = CH[x].CR.EN = 1). - channel in disabled state (CH[x].SR.IDLEF = 1 and CH[x].CR.EN = 0). After writing a RESET, to continue using this channel, the user must explicitly reconfigure the channel including the hardware-modified configuration registers (CH[x].BR1, CH[x].SAR and CH[x].DAR) before enabling again the channel (see the programming sequence in ).

pub const fn susp(&self) -> bool

suspend. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going GPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in .

pub fn set_susp(&mut self, val: bool)

suspend. Writing 1 into the field RESET (bit 1) causes the hardware to de-assert this bit, whatever is written into this bit 2. Else: Software must write 1 in order to suspend an active channel i.e. a channel with an on-going GPDMA transfer over its master ports. The software must write 0 in order to resume a suspended channel, following the programming sequence detailed in .

pub const fn tcie(&self) -> bool

transfer complete interrupt enable

pub fn set_tcie(&mut self, val: bool)

transfer complete interrupt enable

pub const fn htie(&self) -> bool

half transfer complete interrupt enable

pub fn set_htie(&mut self, val: bool)

half transfer complete interrupt enable

pub const fn dteie(&self) -> bool

data transfer error interrupt enable

pub fn set_dteie(&mut self, val: bool)

data transfer error interrupt enable

pub const fn uleie(&self) -> bool

update link transfer error interrupt enable

pub fn set_uleie(&mut self, val: bool)

update link transfer error interrupt enable

pub const fn useie(&self) -> bool

user setting error interrupt enable

pub fn set_useie(&mut self, val: bool)

user setting error interrupt enable

pub const fn suspie(&self) -> bool

completed suspension interrupt enable

pub fn set_suspie(&mut self, val: bool)

completed suspension interrupt enable

pub const fn toie(&self) -> bool

trigger overrun interrupt enable

pub fn set_toie(&mut self, val: bool)

trigger overrun interrupt enable

pub const fn lsm(&self) -> Lsm

Link step mode. First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by CH[x].LLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1.

pub fn set_lsm(&mut self, val: Lsm)

Link step mode. First the (possible 1D/repeated) block transfer is executed as defined by the current internal register file until CH[x].BR1.BNDT[15:0] = 0 and CH[x].BR1.BRC[10:0] = 0 if present. Secondly the next linked-list data structure is conditionally uploaded from memory as defined by CH[x].LLR. Then channel execution is completed. Note: This bit must be written when EN=0. This bit is read-only when EN=1.

pub const fn lap(&self) -> Ap

linked-list allocated port. This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1.

pub fn set_lap(&mut self, val: Ap)

linked-list allocated port. This bit is used to allocate the master port for the update of the GPDMA linked-list registers from the memory. Note: This bit must be written when EN=0. This bit is read-only when EN=1.