Enum stm32_metapac::timer::vals::Ocm
#[repr(u8)]pub enum Ocm {
Show 16 variants
FROZEN = 0,
ACTIVEONMATCH = 1,
INACTIVEONMATCH = 2,
TOGGLE = 3,
FORCEINACTIVE = 4,
FORCEACTIVE = 5,
PWMMODE1 = 6,
PWMMODE2 = 7,
RETRIGERRABLE_OPM_MODE_1 = 8,
RETRIGERRABLE_OPM_MODE_2 = 9,
_RESERVED1 = 10,
_RESERVED2 = 11,
COMBINED_PWM_MODE_1 = 12,
COMBINED_PWM_MODE_2 = 13,
ASYMMETRIC_PWM_MODE_1 = 14,
ASYMMETRIC_PWM_MODE_2 = 15,
}
Variants§
FROZEN = 0
The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the outputs
ACTIVEONMATCH = 1
Set channel to active level on match. OCyREF signal is forced high when the counter matches the capture/compare register
INACTIVEONMATCH = 2
Set channel to inactive level on match. OCyREF signal is forced low when the counter matches the capture/compare register
TOGGLE = 3
OCyREF toggles when TIMx_CNT=TIMx_CCRy
FORCEINACTIVE = 4
OCyREF is forced low
FORCEACTIVE = 5
OCyREF is forced high
PWMMODE1 = 6
In upcounting, channel is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel is inactive as long as TIMx_CNT>TIMx_CCRy else active
PWMMODE2 = 7
Inversely to PwmMode1
RETRIGERRABLE_OPM_MODE_1 = 8
In up-counting mode, the channel is active until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update. In down-counting mode, the channel is inactive until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes inactive again at the next update.
RETRIGERRABLE_OPM_MODE_2 = 9
In up-counting mode, the channel is inactive until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 2 and the channels becomes inactive again at the next update. In down- counting mode, the channel is active until a trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM mode 1 and the channels becomes active again at the next update.
_RESERVED1 = 10
_reserved1
_RESERVED2 = 11
_reserved2
COMBINED_PWM_MODE_1 = 12
tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref.
COMBINED_PWM_MODE_2 = 13
tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref.
ASYMMETRIC_PWM_MODE_1 = 14
tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is counting down.
ASYMMETRIC_PWM_MODE_2 = 15
tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is counting down.
Implementations§
Trait Implementations§
§impl Ord for Ocm
impl Ord for Ocm
§impl PartialOrd for Ocm
impl PartialOrd for Ocm
§fn partial_cmp(&self, other: &Ocm) -> Option<Ordering>
fn partial_cmp(&self, other: &Ocm) -> Option<Ordering>
1.0.0 · source§fn le(&self, other: &Rhs) -> bool
fn le(&self, other: &Rhs) -> bool
self
and other
) and is used by the <=
operator. Read more