Struct stm32_metapac::rcc::regs::Pll1cfgr

#[repr(transparent)]
pub struct Pll1cfgr(pub u32);

RCC PLL configuration register

Tuple Fields

0: u32

Implementations

impl Pll1cfgr

pub const fn pllsrc(&self) -> Pllsrc

PLL entry clock source Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled. In order to save power, when no PLL is used, the value of PLLSRC must be 0.

pub fn set_pllsrc(&mut self, val: Pllsrc)

PLL entry clock source Set and cleared by software to select PLL clock source. These bits can be written only when the PLL is disabled. In order to save power, when no PLL is used, the value of PLLSRC must be 0.

pub const fn pllrge(&self) -> Pllrge

PLL input frequency range Set and reset by software to select the proper reference frequency range used for PLL. This bit must be written before enabling the PLL. 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz

pub fn set_pllrge(&mut self, val: Pllrge)

PLL input frequency range Set and reset by software to select the proper reference frequency range used for PLL. This bit must be written before enabling the PLL. 00-01-10: PLL input (ref1_ck) clock range frequency between 4 and 8 MHz

pub const fn pllfracen(&self) -> bool

PLL fractional latch enable Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator. In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details).

pub fn set_pllfracen(&mut self, val: bool)

PLL fractional latch enable Set and reset by software to latch the content of PLLFRACN into the ΣΠmodulator. In order to latch the PLLFRACN value into the ΣΠmodulator, PLLFRACEN must be set to 0, then set to 1: the transition 0 to 1 transfers the content of PLLFRACN into the modulator (see for details).

pub const fn pllm(&self) -> Pllm

Prescaler for PLL Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). …

pub fn set_pllm(&mut self, val: Pllm)

Prescaler for PLL Set and cleared by software to configure the prescaler of the PLL. The VCO1 input frequency is PLL input clock frequency/PLLM. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0). …

pub const fn pllmboost(&self) -> Pllmboost

Prescaler for EPOD booster input clock Set and cleared by software to configure the prescaler of the PLL, used for the EPOD booster. The EPOD booster input frequency is PLL input clock frequency/PLLMBOOST. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0) and EPOD Boost mode is disabled (see ). others: reserved

pub fn set_pllmboost(&mut self, val: Pllmboost)

Prescaler for EPOD booster input clock Set and cleared by software to configure the prescaler of the PLL, used for the EPOD booster. The EPOD booster input frequency is PLL input clock frequency/PLLMBOOST. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0) and EPOD Boost mode is disabled (see ). others: reserved

pub const fn pllpen(&self) -> bool

PLL DIVP divider output enable Set and reset by software to enable the PLL_p_ck output of the PLL. To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).

pub fn set_pllpen(&mut self, val: bool)

PLL DIVP divider output enable Set and reset by software to enable the PLL_p_ck output of the PLL. To save power, PLLPEN and PLLP bits must be set to 0 when the PLL_p_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).

pub const fn pllqen(&self) -> bool

PLL DIVQ divider output enable Set and reset by software to enable the PLL_q_ck output of the PLL. To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).

pub fn set_pllqen(&mut self, val: bool)

PLL DIVQ divider output enable Set and reset by software to enable the PLL_q_ck output of the PLL. To save power, PLLQEN and PLLQ bits must be set to 0 when the PLL_q_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).

pub const fn pllren(&self) -> bool

PLL DIVR divider output enable Set and reset by software to enable the PLL_r_ck output of the PLL. To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).

pub fn set_pllren(&mut self, val: bool)

PLL DIVR divider output enable Set and reset by software to enable the PLL_r_ck output of the PLL. To save power, PLLRENPLL2REN and PLLR bits must be set to 0 when the PLL_r_ck is not used. This bit can be written only when the PLL is disabled (PLLON = 0 and PLLRDY = 0).

Trait Implementations

impl Clone for Pll1cfgr

fn clone(&self) -> Pll1cfgr

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Pll1cfgr

fn default() -> Pll1cfgr

Returns the “default value” for a type.

impl PartialEq for Pll1cfgr

fn eq(&self, other: &Pll1cfgr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Pll1cfgr

impl Eq for Pll1cfgr

impl StructuralPartialEq for Pll1cfgr