Struct Cr 

#[repr(transparent)]
pub struct Cr(pub u32);

CR register.

Tuple Fields

0: u32

Implementations

impl Cr

pub const fn lsion(&self) -> bool

Internal Low Speed oscillator enable Set and reset by software. Reset source only for this field: PORESETn.

pub fn set_lsion(&mut self, val: bool)

Internal Low Speed oscillator enable Set and reset by software. Reset source only for this field: PORESETn.

pub const fn lsirdy(&self) -> Lsirdy

Internal Low Speed oscillator Ready Set and reset by hardware to indicate when the Low Speed Internal RC oscillator is stable. Reset source only for this field: PORESETn.

pub fn set_lsirdy(&mut self, val: Lsirdy)

Internal Low Speed oscillator Ready Set and reset by hardware to indicate when the Low Speed Internal RC oscillator is stable. Reset source only for this field: PORESETn.

pub const fn lseon(&self) -> bool

External Low Speed Clock enable. Set and reset by software. Reset source only for this field: PORESETn.

pub fn set_lseon(&mut self, val: bool)

External Low Speed Clock enable. Set and reset by software. Reset source only for this field: PORESETn.

pub const fn lserdy(&self) -> Lserdy

External Low Speed Clock ready flag. Set by hardware to indicate that LSE oscillator is stable.

pub fn set_lserdy(&mut self, val: Lserdy)

External Low Speed Clock ready flag. Set by hardware to indicate that LSE oscillator is stable.

pub const fn lsebyp(&self) -> Lsebyp

External Low Speed Clock bypass. Set and reset by software. Reset source only for this field: PORESETn.

pub fn set_lsebyp(&mut self, val: Lsebyp)

External Low Speed Clock bypass. Set and reset by software. Reset source only for this field: PORESETn.

pub const fn lockdet_nstop(&self) -> u8

Lock detector Nstop value When start_stop signal is high; a counter is incremented every 16 MHz clock cycle. When the counter reaches (NSTOP+1) x 64 value, the lock_det signal is set high indicating that the PLL is locked. As soon as the start_stop signal is low the counter is reset to 0.

pub fn set_lockdet_nstop(&mut self, val: u8)

Lock detector Nstop value When start_stop signal is high; a counter is incremented every 16 MHz clock cycle. When the counter reaches (NSTOP+1) x 64 value, the lock_det signal is set high indicating that the PLL is locked. As soon as the start_stop signal is low the counter is reset to 0.

pub const fn hsirdy(&self) -> Hsirdy

Internal High Speed clock ready flag. Set by hardware to indicate that internal RC 64MHz oscillator is stable. This bit is activated only if the RC is enabled by HSION (it is not activated if the RC is enabled by an IP request).

pub fn set_hsirdy(&mut self, val: Hsirdy)

Internal High Speed clock ready flag. Set by hardware to indicate that internal RC 64MHz oscillator is stable. This bit is activated only if the RC is enabled by HSION (it is not activated if the RC is enabled by an IP request).

pub const fn hsepllbufon(&self) -> bool

External High Speed Clock Buffer for PLL RF2G4 enable. Set and reset by software.

pub fn set_hsepllbufon(&mut self, val: bool)

External High Speed Clock Buffer for PLL RF2G4 enable. Set and reset by software.

pub const fn hsipllon(&self) -> bool

Internal High Speed Clock PLL enable.

pub fn set_hsipllon(&mut self, val: bool)

Internal High Speed Clock PLL enable.

pub const fn hsipllrdy(&self) -> Hsipllrdy

Internal High Speed Clock PLL ready flag.

pub fn set_hsipllrdy(&mut self, val: Hsipllrdy)

Internal High Speed Clock PLL ready flag.

pub const fn fmrat(&self) -> Fmrat

Force MR_BLE active transmission status (for debug purpose).

pub fn set_fmrat(&mut self, val: Fmrat)

Force MR_BLE active transmission status (for debug purpose).

pub const fn hseon(&self) -> bool

External High Speed Clock enable. Set and reset by software. in low power mode, HSE is turned off.

pub fn set_hseon(&mut self, val: bool)

External High Speed Clock enable. Set and reset by software. in low power mode, HSE is turned off.

pub const fn hserdy(&self) -> Hserdy

External High Speed Clock ready flag. Set by hardware to indicate that HSE oscillator is stable.

pub fn set_hserdy(&mut self, val: Hserdy)

External High Speed Clock ready flag. Set by hardware to indicate that HSE oscillator is stable.

Trait Implementations

impl Clone for Cr

fn clone(&self) -> Cr

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Cr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Cr

fn default() -> Cr

Returns the “default value” for a type.

impl PartialEq for Cr

fn eq(&self, other: &Cr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Cr

impl Eq for Cr

impl StructuralPartialEq for Cr