Struct Conf
#[repr(transparent)]pub struct Conf(pub u32);Expand description
CONF register.
Tuple Fields§
§0: u32Implementations§
§impl Conf
impl Conf
pub const fn cont(&self) -> bool
pub const fn cont(&self) -> bool
CONT: regular sequence runs continuously when ADC mode is enabled: 0: enable the single conversion: when the sequence is over, the conversion stops 1: enable the continuous conversion: when the sequence is over, the sequence starts again until the software sets the CTRL.STOP_OP_MODE bit.
pub fn set_cont(&mut self, val: bool)
pub fn set_cont(&mut self, val: bool)
CONT: regular sequence runs continuously when ADC mode is enabled: 0: enable the single conversion: when the sequence is over, the conversion stops 1: enable the continuous conversion: when the sequence is over, the sequence starts again until the software sets the CTRL.STOP_OP_MODE bit.
pub const fn sequence(&self) -> bool
pub const fn sequence(&self) -> bool
SEQUENCE: enable the sequence mode (active by default): 0: sequence mode is disabled, only SEQ0 is selected 1: sequence mode is enabled, conversions from SEQ0 to SEQx with x=SEQ_LEN Note: clearing this bit is equivalent to SEQUENCE=1 and SEQ_LEN=0000. Ideally, this bit can be kept high as redundant with keeping high and setting SEQ_LEN=0000.
pub fn set_sequence(&mut self, val: bool)
pub fn set_sequence(&mut self, val: bool)
SEQUENCE: enable the sequence mode (active by default): 0: sequence mode is disabled, only SEQ0 is selected 1: sequence mode is enabled, conversions from SEQ0 to SEQx with x=SEQ_LEN Note: clearing this bit is equivalent to SEQUENCE=1 and SEQ_LEN=0000. Ideally, this bit can be kept high as redundant with keeping high and setting SEQ_LEN=0000.
pub const fn seq_len(&self) -> u8
pub const fn seq_len(&self) -> u8
SEQ_LEN[3:0]: number of conversions in a regular sequence: 0000: 1 conversion, starting from SEQ0 0001: 2 conversions, starting from SEQ0 … 1111: 16 conversions, starting from SEQ0.
pub fn set_seq_len(&mut self, val: u8)
pub fn set_seq_len(&mut self, val: u8)
SEQ_LEN[3:0]: number of conversions in a regular sequence: 0000: 1 conversion, starting from SEQ0 0001: 2 conversions, starting from SEQ0 … 1111: 16 conversions, starting from SEQ0.
pub const fn smps_synchro_ena(&self) -> bool
pub const fn smps_synchro_ena(&self) -> bool
SMPS_SYNCHRO_ENA: synchronize the ADC start conversion with a pulse generated by the SMPS: 0: SMPS synchronization is disabled for all ADC clock frequencies 1: SMPS synchronization is enabled (only when ADC clock is 8 MHz or 16 MHz) Note: SMPS_SYNCHRO_ENA must be 0 when the ADC analog clock is 32 MHz or when PWRC_CR5.NOSMPS = 1.
pub fn set_smps_synchro_ena(&mut self, val: bool)
pub fn set_smps_synchro_ena(&mut self, val: bool)
SMPS_SYNCHRO_ENA: synchronize the ADC start conversion with a pulse generated by the SMPS: 0: SMPS synchronization is disabled for all ADC clock frequencies 1: SMPS synchronization is enabled (only when ADC clock is 8 MHz or 16 MHz) Note: SMPS_SYNCHRO_ENA must be 0 when the ADC analog clock is 32 MHz or when PWRC_CR5.NOSMPS = 1.
pub fn set_op_mode(&mut self, val: u8)
pub fn set_op_mode(&mut self, val: u8)
ADC mode selection (= data path selection).
pub const fn sample_rate_lsb(&self) -> u8
pub const fn sample_rate_lsb(&self) -> u8
SAMPLE_RATE_LSB: Sample Rate LSB This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description. When this field is set to a value different than 0, SMPS synchronization is not feasible. This value is hidden to the user.
pub fn set_sample_rate_lsb(&mut self, val: u8)
pub fn set_sample_rate_lsb(&mut self, val: u8)
SAMPLE_RATE_LSB: Sample Rate LSB This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description. When this field is set to a value different than 0, SMPS synchronization is not feasible. This value is hidden to the user.
pub const fn sample_rate(&self) -> u8
pub const fn sample_rate(&self) -> u8
SAMPLE_RATE[1:0]: conversion rate of ADC (F_ADC): F_ADC = F_ADC_CLK/(16 + 16SAMPLE_RATE_MSB + 4SAMPLE_RATE + SAMPLE_RATE_LSB),where F_ADC_CLK is the analog ADC clock frequency. By default F_ADC_CLK is 16MHz frequency.
pub fn set_sample_rate(&mut self, val: u8)
pub fn set_sample_rate(&mut self, val: u8)
SAMPLE_RATE[1:0]: conversion rate of ADC (F_ADC): F_ADC = F_ADC_CLK/(16 + 16SAMPLE_RATE_MSB + 4SAMPLE_RATE + SAMPLE_RATE_LSB),where F_ADC_CLK is the analog ADC clock frequency. By default F_ADC_CLK is 16MHz frequency.
pub const fn dma_ds_ena(&self) -> bool
pub const fn dma_ds_ena(&self) -> bool
DMA_DS_EN: enable the DMA mode for the Down Sampler data path: 0: DMA mode is disabled 1: DMA mode is enabled.
pub fn set_dma_ds_ena(&mut self, val: bool)
pub fn set_dma_ds_ena(&mut self, val: bool)
DMA_DS_EN: enable the DMA mode for the Down Sampler data path: 0: DMA mode is disabled 1: DMA mode is enabled.
pub const fn dma_df_ena(&self) -> bool
pub const fn dma_df_ena(&self) -> bool
enable DMA mode for Decimation Filter data path.
pub fn set_dma_df_ena(&mut self, val: bool)
pub fn set_dma_df_ena(&mut self, val: bool)
enable DMA mode for Decimation Filter data path.
pub const fn ovr_ds_cfg(&self) -> bool
pub const fn ovr_ds_cfg(&self) -> bool
OVR_DS_CFG: Down Sampler overrun configuration: 0: the previous data is kept, the new one is lost 1: the previous data is lost, the new one is kept.
pub fn set_ovr_ds_cfg(&mut self, val: bool)
pub fn set_ovr_ds_cfg(&mut self, val: bool)
OVR_DS_CFG: Down Sampler overrun configuration: 0: the previous data is kept, the new one is lost 1: the previous data is lost, the new one is kept.
pub const fn ovr_df_cfg(&self) -> bool
pub const fn ovr_df_cfg(&self) -> bool
decimation overrun configuration.
pub fn set_ovr_df_cfg(&mut self, val: bool)
pub fn set_ovr_df_cfg(&mut self, val: bool)
decimation overrun configuration.
pub const fn bit_invert_sn(&self) -> bool
pub const fn bit_invert_sn(&self) -> bool
BIT_INVERT_SN: invert bit to bit the ADC data output (1’s complement) when a single negative input is connected to the ADC: 0: no inversion (default) 1: enable the inversion.
pub fn set_bit_invert_sn(&mut self, val: bool)
pub fn set_bit_invert_sn(&mut self, val: bool)
BIT_INVERT_SN: invert bit to bit the ADC data output (1’s complement) when a single negative input is connected to the ADC: 0: no inversion (default) 1: enable the inversion.
pub const fn bit_invert_diff(&self) -> bool
pub const fn bit_invert_diff(&self) -> bool
BIT_INVERT_DIFF: invert bit to bit the ADC data output (1’s complement) when a differential input is connected to the ADC: 0: no inversion (default) 1: enable the inversion.
pub fn set_bit_invert_diff(&mut self, val: bool)
pub fn set_bit_invert_diff(&mut self, val: bool)
BIT_INVERT_DIFF: invert bit to bit the ADC data output (1’s complement) when a differential input is connected to the ADC: 0: no inversion (default) 1: enable the inversion.
pub const fn adc_cont_1v2(&self) -> bool
pub const fn adc_cont_1v2(&self) -> bool
ADC_CONT_1V2: select the input sampling method: 0: sampling only at conversion start (default) 1: sampling starts at the end of conversion.
pub fn set_adc_cont_1v2(&mut self, val: bool)
pub fn set_adc_cont_1v2(&mut self, val: bool)
ADC_CONT_1V2: select the input sampling method: 0: sampling only at conversion start (default) 1: sampling starts at the end of conversion.
pub const fn vbias_prech_force(&self) -> bool
pub const fn vbias_prech_force(&self) -> bool
possibility to keep the VBIAS_PRECH enabled to deactivate the filter.
pub fn set_vbias_prech_force(&mut self, val: bool)
pub fn set_vbias_prech_force(&mut self, val: bool)
possibility to keep the VBIAS_PRECH enabled to deactivate the filter.
pub const fn sample_rate_msb(&self) -> u8
pub const fn sample_rate_msb(&self) -> u8
SAMPLE_RATE_MSB: Sample Rate MSB This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description.
pub fn set_sample_rate_msb(&mut self, val: u8)
pub fn set_sample_rate_msb(&mut self, val: u8)
SAMPLE_RATE_MSB: Sample Rate MSB This field is an extension of SAMPLE_RATE definition in bits 12,11 of CONF register. It impacts the conversion rate of ADC (F_ADC). See SAMPLE_RATE bits for the full description.