Struct Cr 

#[repr(transparent)]
pub struct Cr(pub u32);

CR register.

Tuple Fields

0: u32

Implementations

impl Cr

pub const fn disable(&self) -> bool

Disable Bit DISABLE can be used for reading or setting the state of the TRNG core. The value read is always the one available at the rng core clock domain. When changing the value, the change is effective when the value read is the same as the one written.

pub fn set_disable(&mut self, val: bool)

Disable Bit DISABLE can be used for reading or setting the state of the TRNG core. The value read is always the one available at the rng core clock domain. When changing the value, the change is effective when the value read is the same as the one written.

pub const fn clr_revclk_flag(&self) -> ClrRevclkFlag

Reset reveal clock error flags when writing a ‘1’ without resetting the whole TRNG. When writing a 1, the value remains until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset.

pub fn set_clr_revclk_flag(&mut self, val: ClrRevclkFlag)

Reset reveal clock error flags when writing a ‘1’ without resetting the whole TRNG. When writing a 1, the value remains until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset.

pub const fn rst_health_flags(&self) -> RstHealthFlags

Reset Health error flags when writing a ‘1’ without resetting the whole TRNG. When writing a 1, the value remains until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset.

pub fn set_rst_health_flags(&mut self, val: RstHealthFlags)

Reset Health error flags when writing a ‘1’ without resetting the whole TRNG. When writing a 1, the value remains until it is seen by RNG core clock domain after resynchronization. Then it is automatically reset.

pub const fn clkdiv(&self) -> u16

Sampling Clock Enable Divider. CLKDIV[15:0] control the sampling clock enable divider, dividing by a factor equal to CLKDIV[15:0]

• 1, values being in the range of 1 to 65536.

pub fn set_clkdiv(&mut self, val: u16)

Sampling Clock Enable Divider. CLKDIV[15:0] control the sampling clock enable divider, dividing by a factor equal to CLKDIV[15:0]

• 1, values being in the range of 1 to 65536.

Trait Implementations

impl Clone for Cr

fn clone(&self) -> Cr

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Cr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Default for Cr

fn default() -> Cr

Returns the “default value” for a type.

impl PartialEq for Cr

fn eq(&self, other: &Cr) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Cr

impl Eq for Cr

impl StructuralPartialEq for Cr