Struct Cfgr

#[repr(transparent)]
pub struct Cfgr(pub u32);

Expand description

CFGR register.

Tuple Fields§

§0: u32

Implementations§

§

impl Cfgr

pub const fn smpsinv(&self) -> Smpsinv

bit to control inversion of the SMPS clock.

pub fn set_smpsinv(&mut self, val: Smpsinv)

bit to control inversion of the SMPS clock.

pub const fn hsesel(&self) -> Hsesel

Clock source selection request:.

pub fn set_hsesel(&mut self, val: Hsesel)

Clock source selection request:.

pub const fn stophsi(&self) -> Stophsi

Stop HSI clock source request.

pub fn set_stophsi(&mut self, val: Stophsi)

Stop HSI clock source request.

pub const fn hsesel_status(&self) -> HseselStatus

Clock source selection Status.

pub fn set_hsesel_status(&mut self, val: HseselStatus)

Clock source selection Status.

pub const fn clksysdiv(&self) -> u8

CLKSYSDIV: system clock divided factor from HSI_64M. 000: system clock frequency is 64 MHz (not available when HSESEL=1) 001: system clock frequency is 32 MHz 010: system clock frequency is 16 MHz 011: system clock frequency is 8 MHz * 100: system clock frequency is 4 MHz * 101: system clock frequency is 2 MHz * 110: system clock frequency is 1 MHz * 111: not used. *: If RCC_APB2ENR.MRBLEEN bit is set, writing in CLKSYSDIV one of those values is replaced by a 010b = 16 MHz writing at hardware level. Warning: if the software programs the 64 MHz frequency target while the RCC_CFGR.HSESEL=1, the hardware will switch the system clock tree on HSI64MPLL again (and restart HSIPLL64M analog block if RCC_CFGR.STOPHSI=1) To switch the system frequency between 64 / 32 / 16 MHz without risk when the MR_BLE is used, prefer the RCC_CSCMDR register to change the system frequency. the MR_BLE frequency must always be equal or less than the CPU/system clock to have functional radio.

pub fn set_clksysdiv(&mut self, val: u8)

CLKSYSDIV: system clock divided factor from HSI_64M. 000: system clock frequency is 64 MHz (not available when HSESEL=1) 001: system clock frequency is 32 MHz 010: system clock frequency is 16 MHz 011: system clock frequency is 8 MHz * 100: system clock frequency is 4 MHz * 101: system clock frequency is 2 MHz * 110: system clock frequency is 1 MHz * 111: not used. *: If RCC_APB2ENR.MRBLEEN bit is set, writing in CLKSYSDIV one of those values is replaced by a 010b = 16 MHz writing at hardware level. Warning: if the software programs the 64 MHz frequency target while the RCC_CFGR.HSESEL=1, the hardware will switch the system clock tree on HSI64MPLL again (and restart HSIPLL64M analog block if RCC_CFGR.STOPHSI=1) To switch the system frequency between 64 / 32 / 16 MHz without risk when the MR_BLE is used, prefer the RCC_CSCMDR register to change the system frequency. the MR_BLE frequency must always be equal or less than the CPU/system clock to have functional radio.

pub const fn clksysdiv_status(&self) -> u8

CLKSYSDIV_STATUS: system clock frequency status Set and cleared by hardware to indicate the actual system clock frequency. This register must be read to be sure that the new frequency, selected by CLKSYSDIV, has been applied. 000: system clock frequency is 64 MHz 001: system clock frequency is 32 MHz 010: system clock frequency is 16 MHz 011: system clock frequency is 8 MHz 100: system clock frequency is 4 MHz 101: system clock frequency is 2 MHz 110: system clock frequency is 1 MHz 111: not used. The actual clock frequency switching can be delayed of up to 128 system clock cycles, depending on the RCC internal counter status at the moment the new CLKSYSDIV is applied.

pub fn set_clksysdiv_status(&mut self, val: u8)

CLKSYSDIV_STATUS: system clock frequency status Set and cleared by hardware to indicate the actual system clock frequency. This register must be read to be sure that the new frequency, selected by CLKSYSDIV, has been applied. 000: system clock frequency is 64 MHz 001: system clock frequency is 32 MHz 010: system clock frequency is 16 MHz 011: system clock frequency is 8 MHz 100: system clock frequency is 4 MHz 101: system clock frequency is 2 MHz 110: system clock frequency is 1 MHz 111: not used. The actual clock frequency switching can be delayed of up to 128 system clock cycles, depending on the RCC internal counter status at the moment the new CLKSYSDIV is applied.

pub const fn smpsdiv(&self) -> Smpsdiv

SMPS clock prescaling factor to generate 4MHz or 8MHz.

pub fn set_smpsdiv(&mut self, val: Smpsdiv)

SMPS clock prescaling factor to generate 4MHz or 8MHz.

pub const fn lpuclksel(&self) -> Lpuclksel

Selection of LPUART clock:.

pub fn set_lpuclksel(&mut self, val: Lpuclksel)

Selection of LPUART clock:.

pub const fn clkslowsel(&self) -> Clkslowsel

slow clock source selection Set by software to select the clock source. This is no glitch free mechanism Reset source only for this field: PORESETn.

pub fn set_clkslowsel(&mut self, val: Clkslowsel)

slow clock source selection Set by software to select the clock source. This is no glitch free mechanism Reset source only for this field: PORESETn.

pub const fn ioboosten(&self) -> bool

IO BOOSTER enable Set and reset by software.

pub fn set_ioboosten(&mut self, val: bool)

IO BOOSTER enable Set and reset by software.

pub const fn ioboostclkexten(&self) -> bool

IO BOOSTER clock enable as external clock Set and reset by software.

pub fn set_ioboostclkexten(&mut self, val: bool)

IO BOOSTER clock enable as external clock Set and reset by software.

pub const fn lcoen(&self) -> bool

LCO output enable.

pub fn set_lcoen(&mut self, val: bool)

LCO output enable.

pub const fn spi3i2sclksel(&self) -> Spiisclksel

Selection of I2S1 clock: 1x:64MHz peripheral clock.

pub fn set_spi3i2sclksel(&mut self, val: Spiisclksel)

Selection of I2S1 clock: 1x:64MHz peripheral clock.

pub const fn spi2i2sclksel(&self) -> bool

Selection of I2S clock: 1x:64MHz peripheral clock.

pub fn set_spi2i2sclksel(&mut self, val: bool)

Selection of I2S clock: 1x:64MHz peripheral clock.

pub const fn lcosel(&self) -> Lcosel

Low speed Configurable Clock Output Selection. Set and reset by software. Glitches propagation possible. Reset source only for this field: PORESETn.

pub fn set_lcosel(&mut self, val: Lcosel)

Low speed Configurable Clock Output Selection. Set and reset by software. Glitches propagation possible. Reset source only for this field: PORESETn.

pub const fn mcosel(&self) -> Mcosel

Main Configurable Clock Output Selection. Set and reset by software. Glitches propagation possible.

pub fn set_mcosel(&mut self, val: Mcosel)

Main Configurable Clock Output Selection. Set and reset by software. Glitches propagation possible.

pub const fn ccopre(&self) -> Ccopre

Configurable Clock Output Prescaler. Set and reset by software. Glitches propagation if CCOPRE is modified after CCO output is enabled. Others: not used.

pub fn set_ccopre(&mut self, val: Ccopre)

Configurable Clock Output Prescaler. Set and reset by software. Glitches propagation if CCOPRE is modified after CCO output is enabled. Others: not used.