Struct stm32_metapac::rcc::regs::Ahb4smenr
#[repr(transparent)]pub struct Ahb4smenr(pub u32);
Expand description
RCC AHB4 peripheral clocks enable in Sleep and Stop modes register
Tuple Fields§
§0: u32
Implementations§
§impl Ahb4smenr
impl Ahb4smenr
pub const fn pwrsmen(&self) -> bool
pub const fn pwrsmen(&self) -> bool
PWR bus clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub fn set_pwrsmen(&mut self, val: bool)
pub fn set_pwrsmen(&mut self, val: bool)
PWR bus clock enable during Sleep and Stop modes Set and cleared by software. Can only be accessed secure when one or more features in the PWR is/are secure. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV.
pub const fn adc4smen(&self) -> bool
pub const fn adc4smen(&self) -> bool
ADC4 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes.
pub fn set_adc4smen(&mut self, val: bool)
pub fn set_adc4smen(&mut self, val: bool)
ADC4 bus and kernel clocks enable during Sleep and Stop modes Set and cleared by software. Access can be secured by GTZC_TZSC ADC4SEC. When secure, a non-secure read/write access is RAZ/WI. It does not generate an illegal access interrupt. This bit can be protected against unprivileged access when secure with RCC SPRIV or when non-secure with RCC NSPRIV. Note: This bit must be set to allow the peripheral to wake up from Stop modes.