Struct stm32_metapac::syscfg::regs::Mesr
#[repr(transparent)]pub struct Mesr(pub u32);
Expand description
memory erase status register
Tuple Fields§
§0: u32
Implementations§
§impl Mesr
impl Mesr
pub const fn mclr(&self) -> bool
pub const fn mclr(&self) -> bool
Device memories erase status This bit is set by hardware when SRAM2, ICACHE, PKA SRAM erase is completed after power-on reset or tamper detection (refer to Section�75: Tamper and backup registers (TAMP) for more details). This bit is not reset by system reset and is cleared by software by writing 1 to it.
pub fn set_mclr(&mut self, val: bool)
pub fn set_mclr(&mut self, val: bool)
Device memories erase status This bit is set by hardware when SRAM2, ICACHE, PKA SRAM erase is completed after power-on reset or tamper detection (refer to Section�75: Tamper and backup registers (TAMP) for more details). This bit is not reset by system reset and is cleared by software by writing 1 to it.
pub const fn ipmee(&self) -> bool
pub const fn ipmee(&self) -> bool
ICACHE and PKA SRAM erase status This bit is set by hardware when ICACHE and PKA SRAM erase is completed after potential tamper detection (refer to Section�75: Tamper and backup registers (TAMP) for more details). This bit is cleared by software by writing 1 to it.
pub fn set_ipmee(&mut self, val: bool)
pub fn set_ipmee(&mut self, val: bool)
ICACHE and PKA SRAM erase status This bit is set by hardware when ICACHE and PKA SRAM erase is completed after potential tamper detection (refer to Section�75: Tamper and backup registers (TAMP) for more details). This bit is cleared by software by writing 1 to it.