Struct stm32_metapac::rcc::regs::Cfgr2

#[repr(transparent)]
pub struct Cfgr2(pub u32);

RCC clock configuration register 2

Tuple Fields

0: u32

Implementations

impl Cfgr2

pub const fn hpre(&self) -> Hpre

AHB1, AHB2 and AHB4 prescaler Set and cleared by software to control the division factor of the AHB1, AHB2 and AHB4 clock (hclk1). The software must limit the incremental frequency step by setting these bits correctly to ensure that the hclk1 maximum incremental frequency step does not exceed the maximum allowed incremental frequency step (for more details, refer to Table�99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xx: hclk1 = SYSCLK not divided

pub fn set_hpre(&mut self, val: Hpre)

AHB1, AHB2 and AHB4 prescaler Set and cleared by software to control the division factor of the AHB1, AHB2 and AHB4 clock (hclk1). The software must limit the incremental frequency step by setting these bits correctly to ensure that the hclk1 maximum incremental frequency step does not exceed the maximum allowed incremental frequency step (for more details, refer to Table�99: SYSCLK and bus maximum frequency). After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value is taken into account. 0xx: hclk1 = SYSCLK not divided

pub const fn ppre1(&self) -> Ppre

APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (pclk1). 0xx: pclk1 = hclk1 not divided

pub fn set_ppre1(&mut self, val: Ppre)

APB1 prescaler Set and cleared by software to control the division factor of the APB1 clock (pclk1). 0xx: pclk1 = hclk1 not divided

pub const fn ppre2(&self) -> Ppre

APB2 prescaler Set and cleared by software to control the division factor of the APB2 clock (pclk2). 0xx: pclk2 = hclk1 not divided

pub fn set_ppre2(&mut self, val: Ppre)

APB2 prescaler Set and cleared by software to control the division factor of the APB2 clock (pclk2). 0xx: pclk2 = hclk1 not divided

Trait Implementations

impl Clone for Cfgr2

fn clone(&self) -> Cfgr2

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Default for Cfgr2

fn default() -> Cfgr2

Returns the “default value” for a type.

impl PartialEq for Cfgr2

fn eq(&self, other: &Cfgr2) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Cfgr2

impl Eq for Cfgr2

impl StructuralPartialEq for Cfgr2